Cmsemicon SC8F577 Series - Page 110

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16.2 Clock Precision for Asynchronous Operations
The output of the internal oscillation circuit (INTOSC) is calibrated by the manufacturer. But when VDD
or temperature changes, INTOSC will have a frequency shift, which will directly affect the asynchronous
baud rate. The baud rate clock can be adjusted by the following methods, but some type of reference is
required clock source.
16.3 USART Related Register
TXSTA：transmit status and control register (117H)
117H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TXSTA
CSRC
TX9EN
TXEN(1)
SYNC
SCKP
STOPBIT
TRMT
TX9D
read/write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Reset value
0
0
0
0
0
0
1
0
Bit7
CSRC0:
clock sources election bit;
Asynchronous mode:
Any value;
Synchronous mode:
1=master control mode (internal BRG generate clock signal);
0=slave mode (external clock source generate clock).
Bit6
TX9EN:
9-bit transmit enable bit;
1=
Select 9-bit transmit;
0=
Select 8-bit transmit.
Bit5
TXEN:
Transmit enable bit (1);
1=
Enable transmit;
0=
Disable transmit.
Bit4
SYNC:
USART mode selection bit;
1=
Synchronous mode;
0=
Asynchronous mode.
Bit3
SCKP:
Synchronous clock polarity selection bit.
Asynchronous mode:
1= Invert the level of the data character and transmit to the TX/CK pin;
0= Directly transmit data character to TX/CK pin.
Synchronous mode:
0= Data is transmitted on the rising edge of clock;
1= Data is transmitted on the falling edge of clock.
Bit2
STOPBIT:
Stop bit selection (only valid for asynchronous transmit), this bit needs to
write to 0 when giving data for transmit by judge TRMT=1.
1=
1 stop bit;
0=
2 stop bits.
Bit1
TRMT:
Transmit shift register status bit;
1=
TSR empty;
0=
TSR full.
Bit0
TX9D:
9
th
bit of Transmit data.
Can be address/data bit or parity check bit.
Note:
1) In synchronous mode, SREN/CREN will invert the value of TXEN.
2) When sending data by judging TRMT=1, STOPBIT needs to write 0.