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Cmsemicon SC8F577 Series - ADC Interrupt; Output Formatting

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V1.8
SC8F577x
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10.2.6 ADC Interrupt
ADC mod allows an interrupt to be generated after the completion of the analog-to-digital conversion.
The ADC interrupt flag bit is the ADIF bit in PIR1 register. The ADC interrupt enable bit is the ADIE bit in PIE1
register. The ADIF bit must be cleared by software. The ADIF bit after each conversion is completed Will be
set to 1, regardless of whether ADC interrupt is allowed.
Interrupts can be generated regardless of whether the device is in working mode or sleep mode. If the
device is in sleep mode, this interrupt can wake up the device. When the device is awakened from sleep state,
the next instruction after the STOP instruction is always executed. If the user tries to wake the device from
sleep mode and resume code execution in order, the global interrupt must be disabled. If the global interrupt
is allowed, the program will jump to the interrupt service routine to run the code.
10.2.7 Output Formatting
The result of 12-bit A/D conversion can be in two formats: left-justified or right-justified. The output format
is controlled by the ADFM bit in ADCON1 register.
When ADFM=0, the AD conversion result is left aligned and the AD conversion result is 12Bit; when
ADFM=1, the AD conversion result is right aligned, and the AD conversion result is 10 Bit.

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