18.3.9 Clock Arbitration
If during any receive, transmit, or repeated start/stop conditions, the master device pulls up the SCL pin
(allowing the SCL pin to float high), clock arbitration will occur. If the SCL pin is allowed to float high, the baud
rate generator (BRG) will pause counting until the SC L pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator will be reloaded with the contents of IICADD<6:0> and start counting.
This can ensure that when the external device pulls the clock low, the SCL always maintains high for at least
one BRG full return period.
T
BRG
T
BRG
T
BRG
BRG overflows, release SCL, if SCL=1,
use IICADD<6:0> to load BRG and start
BRG to count to measure high level time
BRG overflow occurs, the release SCL,
the slave device holding SCL low
SCL=1, BR starts to count the high level
time of the clock
The SCL line is sampled once in each
machine cycle (T
OSC
*4) to keep BRG in the
waiting state until SCL is sampled at high level
SCL
SDA
Fig 18-11: clock arbitration in master control transmit mode
18.3.10 Multi Master Mode
In multi-master mode, it can be determined when the bus is free by generating interrupt when the start
and stop conditions are detected. The stop (P) bit and the start (S) bit are cleared when reset or disable IIC
mod. When the P bit is set to 1, you can get control of the I
2
C bus; otherwise, the bus is in an idle state, and
the P and S bits are cleared. When the bus is busy, if a stop condition occurs, an interrupt will be generated
(if IIC interrupt is allowed).
When working in multi-master mode, you must monitor the SDA line for arbitration to see if the signal
level is the expected output level. This check is done by hardware, and the result is placed in the BCLIF bit.
Arbitration may fail under the following conditions:
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