18.3.11 Multi Master Communication, Bus Conflict and Bus Arbitration
Multi-master mode is supported by bus arbitration. When the master device outputs the address/data bit
to the SDA pin, if one master device outputs 1 on SDA by floating the SDA pin to high level, and the other
master device outputs 0, bus arbitration will occur. If the expected data on the SDA pin is 1, and the data
actually sampled on the SDA pin is 0, a bus conflict has occurred. The master device will set the bus conflict
interrupt flag bit IICIF to 1, and reset the I
2
C port to idle state.
If a bus conflict occurs during the transmit process, the transmit stops, the BF flag bit is cleared, the SDA
and SCL lines are pulled high, and IICBUF is allowed to be written. After the bus conflict interrupt service
program is executed, if the I
2
C bus is free, user can resume communication by issuing a start condition. If a
bus conflict occurs during the start, repeated start, stop, or response condition, the condition is aborted, the
SDA and SCL lines are pulled high, and the corresponding control bit in the IICCON2 register is cleared. After
executing the bus conflict interrupt service program, if the I
2
C bus is free, the user can resume communication
by issuing a start condition. The master device will continue to monitor SDA and SCL pin. If a stop condition
occurs, the IICIF bit will be set to 1. No matter what bus occurs What is the progress of the transmit during
conflict, writing IICBUF will start transmitting data from the first data bit.
In multi-master mode, the interrupt can be generated when the start and stop conditions are detected to
determine when the bus is free. When the P bit is set to 1, you can obtain control of the I2C bus, otherwise
the bus is free and the S and P bits are cleared.
18.4 Slave Mode
In slave mode, SCL pin and SDA pin must be configured as input. When needed (such as from the
transmitter), the IIC mod will use output data to rewrite the input state.
When the address matches or the data transmitted after the address matches is received, the hardware
will automatically generate an acknowledge (ACK) pulse, and load the data received in the IICSR register at
the time into the IICBUF register.
As long as one of the following conditions is met, IIC mod will not generate this ACK pulse:
- The buffer full flag bit BF (IICCON register) is 1 before the received data to be transmitted.
- Before receiving the transmitted data, the overflow flag bit IICOV (IICCON register) has been set 1
In this case, the value of IICSR register will not be loaded into IICBUF, but the IICIF bit of PIR1 register
will be set to 1. The BF bit is cleared by reading the IICBUF register, and the IICOV bit is cleared by software.
To ensure normal operation, SCL clock input must meet the minimum high-level time and minimum low-
level time requirements.
To Next Page