5. Sleep Mode
5.1 Enter Sleep Mode
System can enter sleep mode when executing STOP instructions. If WDT enabled, then:
◆ WDT is cleared and continue to run.
◆ PD bit in STATUS register is cleared.
◆ TO bit set to 1.
◆ Turn off oscillator driver device.
◆ I/O port keep at the status before STOP (driver is high level, low lower, or high impedance).
Under sleep mode, to avoid current consumption, all I/O pin should keep at VDD or GND to make sure
no external circuit is consuming the current from I/O pin. To avoid input pin, suspend and invoke current, high
impedance I/O should be pulled to high or low level externally. Internal pull up resistance should also be
considered.
5.2 Awaken from Sleep Mode
Awaken through any of the following events:
1. Watchdog timer awake (WDT force enable)
2. PORTA/PORTB/ PORTC electrical level interrupt
3. Other peripheral interrupt
The above 2 events are regards as the extension of the execution of the program. TO and PD bit in
STATUS register are used to find the reason for reset. PD is set to 1 when power on and clear to 0 when
STOP instruction is executing.TO is cleared when WDT awaken happens.
When executes STOP instructions, next instruction (PC+1)is withdrawal first. If it is intended to awaken
the system using interrupt, the corresponding enable bit should be set to 1 for the interrupt. Awaken is not
related to GIE bit. If GIE is cleared, system will continue to execute the instruction after STOP instruction, and
then jump to interrupt address (0004h) to execute. To avoid instruction after STOP instruction being executed,
user should put one NOP instruction after STOP instruction. When system is awakening from sleep mode,
WDT will be cleared to 0 and has nothing to do with the reason for awakening.
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