5.3 Interrupt Awakening
When forbidden overall interrupt ( GIE clear), and there exist 1 interrupt source with its interrupt enable
bit and indication bit set to 1, one event from the following will happen:
- If interrupt happens before STOP instructions, then STOP instruction is executed as NOP instructions.
Hence, WDT and its pre-scaler and post-scaler will not be cleared, and TO bit will not be set to 1, PD
will not be cleared to 0.
- If interrupt happens during or after STOP instruction, then system is awakening from sleep mode.
STOP will be executed before system being fully awaken. Hence, WDT and its pre-scaler, post-scaler
will be cleared to, TO bit set to 1 and PD bit cleared to 0. Even if the indication bit is 0 before executing
the STOP instruction, it can be set to 1 before STOP instruction is finished. To check whether STOP
is executed, PD bit can be checked, if is 1, then STOP instruction is executed as NOP. Before
executing STOP instruction, 1 CLRWDT instruction must be excited to make sure WDT is cleared.
5.4 Sleep Mode Application
Before system enters sleep mode, if user wants small sleep current, please check all I/O status. If
suspended I/O port is required by user, set all suspended ports as output to make sure each I/O has a fixed
status and avoid increasing sleep current when I/O is input；turn off AD and other peripherals mod；WDT
functions can be turned off to decrease the sleep current.
example：procedures for entering sleep mode
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