Cmsemicon SC8F577 Series - Page 76

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10.2.5 Converter clock
The ADCS bit of the ADCON0 and ADCON1 register can be set by software to select the clock source
for conversion. There are 7 possible clock frequencies to choose from:
◆
F
OSC
/2
◆
F
OSC
/32
◆
F
OSC
/4
◆
F
OSC
/64
◆
F
OSC
/8
◆
F
OSC
/128
◆
F
OSC
/16
The time to complete one-bit conversion is defined as TAD. A complete 12-bit conversion requires 16
TAD periods.
Must comply with the corresponding TAD specification to get the correct conversion result. The following
table is an example of correct selection of ADC clock.
Relationship between period of ADC clock (TAD) and the operating frequency of device (VDD=3.3V).
Period of ADC clock
Once AD conversion time
ADC clock
source
ADCS<2:0>
F
OSC
= 16MHz
F
OSC
= 8MHz
F
OSC
/2
001
2μs
4μs
F
OSC
/4
010
4μs
8μs
F
OSC
/8
011
8μs
16μs
F
OSC
/16
100
16μs
32μs
F
OSC
/32
101
32μs
64μs
F
OSC
/64
110
64μs
128μs
F
OSC
/128
111
128μs
256μs
Note: It is recommended not to use the values in the shaded table.
For different reference voltages and different VDDs, please refer to the following table to set a reasonable
frequency division.
Reference
voltage (V)
Operating
voltage (V)
Fastest frequency division setting
Conversion rate (ksps)
F
OSC
= 16MHz
F
OSC
= 8MHz
VDD
2.6~3.6
F
OSC
/4
F
OSC
/2
250
VDD
1.8~2.6
F
OSC
/8
F
OSC
/4
125
2.4
2.6~3.6
F
OSC
/8
F
OSC
/4
125
2.4
1.8~2.6
F
OSC
/16
F
OSC
/8
62.5
2.0
2.6~3.6
F
OSC
/8
F
OSC
/4
125
2.0
1.8~2.6
F
OSC
/16
F
OSC
/8
62.5
1.2
2.6~3.6
F
OSC
/64
F
OSC
/32
15.6
1.2
1.8~2.6
F
OSC
/128
F
OSC
/64
7.8