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V1.8
SC8F577x
124 / 181
www.mcu.com.cn
17.4 Enable SPI I/O
To enable the serial port, the SPI enable bit SPIEN of the SPICON register must be set to 1. To reset or
reconfigure the SPI mode, first clear the SPIEN bit, reinitialize the SPICON register, and then set the SPIEN
bit to 1. This will set MOSI, MISO, The SCK and SS pins are configured as serial port pins. To use these pins
as serial ports, the data direction bits (in the TRIS register) must be programmed correctly, as follows:
SDI controlled by SPI mod;
The TRIS bit of MOSI must be cleared (master control mode);
The TRIS bit of MISO must be cleared (slave mode);
The TRIS bit of SCK (master control mode) must be cleared;
The TRIS bit of SCK (slave mode) must be set to 1;
The TRIS of SS (slave mode) must be set to 1.
For any unwanted serial port function, you can skip it by setting the corresponding data direction (TRIS)
register to the opposite value.
17.5 Master Control Mode
The master device controls SCK, so it can start data transmission at any time. The master device
determines when the slave device should broadcast data according to the software protocol.
In master control mode, once data is written into the SPIBUF register, it will start to transmit or receive. If
SPI is only used as a receiver, you can disable SDO output (program it to input). SPISR register is connected
to the SDI pin at the set clock rate the signal performs continuous shift input. After each byte receive is
completed, it will be treated as a normal receive byte and loaded into the SPIBUF register (corresponding to
interrupt and status position 1). This can be used as a line activity monitoring mode, which is very useful.
The clock polarity can be selected by programming the CKP bit of the SPICON register accordingly.
Figure 17-2, Figure 17-3, Figure 17-4, and Figure 17-5 show the SPI communication waveforms, where MSb
is first transmitted. In master control mode, the SPI clock rate (bit rate) can be programmed by the user to one
of the following rates:
F
SYS
/4 (or TCY)
F
SYS
/16 (or 4.TCY)
F
SYS
/64 (or 16.TCY)
TIMER2 output/2

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