If the SCL and SDA pins have been programmed as input pins (set the corresponding TRIS bit to 1),
selecting any I
2
C mode and IICEN bit as 1 will force the SCL and SDA pins to be open drain.
18.2 IIC Related Register
IICSTAT: IIC status register (10FH)
master control mode idle bit
(Only the master control mode is valid, all master control operations
can use this bit to determine whether to terminate)
No master control operation on the bus
The master control operation is in progress on the bus
Indicates that the last receive or transmit byte is data.
Indicates that the last receive or transmit byte is address.
Stop bit (this bit is cleared when IIC mode is disabled (IICEN is
cleared)).
Indicates that the stop bit was finally detected (the bit is 0 when reset).
Indicates that the stop bit was not detected at the end.
Start bit (this bit is cleared when disable IIC mode (IICEN is cleared)).
Indicates that the start bit was finally detected (the bit is 0 when reset).
The start bit was not detected at the end.
Read/write bit.
This bit is used to save the R/W bit information after the last address
match. This bit is only valid from the address match to the next start bit,
stop bit or non-ACK bit.
0= not transmitting.
The result of logic OR operation between this bit and SEN, RSEN,
PEN, RCEN or ACKEN will indicate whether IIC is in idle mode.
1= receive complete, IICBUF full.
0= receive not complete, IIC BUF empty.
1 = data transmitting (not including ACK and stop bit), IICBUF full.
0 = data transmit complete (not including ACK and stop bit), IICBUF
empty.
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