18.3.4 I
2
C Master Control Mode Receive
By programming receive enable bit RCEN (IICCON2 register) to enable master control mode receive.
The baud rate generator starts counting, and each time the count returns, the state of the SCL pin changes
(from high to low or from low to high), and data is shifted into IICSR. After the falling edge of the eighth clock,
the receive enable flag bit is automatically cleared, the content of IICSR is loaded into IICBUF, the BF flag bit
is set to 1, the IICIF flag bit is set to 1, the baud rate generator pauses counting, and the SCL remains at low
level. At this time, IIC is in idle state, waiting for the next command. When the CPU reads the buffer, the BF
flag bit will be automatically cleared. By setting the response sequence enable bit ACKEN (IICCON2 register)
to 1, the user can end the receive transmit response bit.
18.3.4.1 BF Status Indication
When receiving, when the address or data byte is loaded from IICSR into IICBUF, the BF bit is set to 1,
and the BF bit is cleared when reading the IICBUF register.
18.3.4.2 WCOL Status Indication
If the user writes IICBUF during the receive process (that is, when the IICSR is still moving into the data
byte), the WCOL bit is set to 1, and the buffer content remains unchanged (no write operation has occurred).
Write IICCON2<0> (SEN=1)
Start condition start
SEN=0
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
654 7
3
2
1
8 9 654 7
3
2
1
8 9
Send address to slave
Write 7-bit address and R/W into IICBUF
Start sending
R/W=0
ACK=0
From the slave, clear the ACKSTAT bit
(IICCON2<6>)
send data
ACK
ACKSTAT=1 in IICCON2
S
P
When the CPU responds to IICIF, SCL remains low
Cleared in IIC interrupt service routine
Clear with software
Write IICBUF in software
Clear with software
Write IICBUF
After the start condition, clear SEN by hardware
SDA
SCL
IICIF
BF
SEN
PEN
R/W
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