6.4.4 PORTC Pull up Resistance
Each PORTC pin has an internal weak pull up that can be individually configured. The control bits
WPUC<3:0> enable or disable each weak pull up.
PORTC pull up resistance register WPUC (99H)
Note:
1) WPUC[3] will invalid if RC3 is configured as reset input, and the weak pull up of RC3 will force to
valid.
2) If pin is configured as output, weak pull up will be automatically disabled.
6.4.5 PORTC Level Change Interrupt
All PORTC pins can be individually configured as level change interrupt pins. The control bit IOCC<1:0>
allows or disables the interrupt function of each pin. Disable pin level change interrupt function when power
on reset.
For the pin that has allowed level change interrupt, compare the value on the pin with the old value
latched when PORTC was read last time. Perform a logical OR operation with the output "mismatch" of the
last read operation to set the PORTC level change interrupt flag (RCCIF) as 1.
This interrupt can wake up the device from sleep mode, and the user can clear the interrupt in the interrupt
service program in the following ways:
-Read or write to PORTC. This will end the mismatch state of the pin level.
-Clear the flag bit RCCIF.
The mismatch status will continuously set the RCCIF flag bit as 1. Reading or writing PORTC will end the
mismatch state and allow the RCCIF flag to be cleared. The latch will keep the last read value from the under
voltage reset. After reset, if the mismatch still exists, the RCCIF flag will continue to be set as 1.
Note: If the level of the I/O pin changes during the read operation (beginning of the Q2 cycle), the
RCCIF interrupt flag bit will not be set as 1. In addition, since reading or writing to a port affects
all bits of the port, special care must be taken when using multiple pins in interrupt-on-change
mode. When dealing with the level change of one pin, you may not notice the level change on
the other pin.
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