Cmsemicon SC8F577 Series - Page 80

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SC8F577x
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10.4 ADC Related Register
There are mainly 4 registers related to AD conversion, namely control register ADCON0 and ADCON1,
data register ADRESH and ADRESL.
AD control register ADCON0 (9DH)
9DH
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADCON0
ADCS1
ADCS0
CHS3
CHS2
CHS1
CHS0
GO/DONE









ADON
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit6
ADCS<1:0>:
A/D conversion clock selection bit.
ADCS<2:0>
ADCS2 in ADCON1 register
000=
Reserved
001=
FOSC/2
010=
FOSC/4
011=
FOSC/8
100=
FOSC/16
101=
FOSC/32
110=
FOSC/64
111=
FOSC/128
Bit5~Bit2
CHS<3:0>:
Analog channel selection bit.
CHS<4:0>
CHS4 in ADCON1 register
00000=
AN0
00001=
AN1
00010=
AN2
00011=
AN3
…
…
10000=
AN16
10001=
AN17
10010=
AN18
10011=
Fixed reference voltage（1.2V）
10100=
PGA output voltage
Other=
Reserved
Bit1
GO/DONE









:
A/D conversion status bit.
1=
A/D conversion is in progress. Set this bit to 1 to start A/D conversion. When A/D
conversion is completed, this bit is automatically cleared by hardware.
At least wait for 2 TAD times to start AD conversion again when GO/DONE









bit change from
1 to 0 or ADIF change from 0 to 1.
0=
A/D conversion complete or not in progress.
Bit0
ADON:
ADC enable bit.
1=
Enable ADC；
0=
Disable ADC, not consuming current.