CHAPTER 2 –Ha
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SPI-6941-LV 13
• High performance CPU Interface
Supports Socket-370 processors
66 / 100 /133 MHz CPU Front Side BUS (FSB)
Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within an
between clocking regions
Five outstanding transactions
Supports WC (Write Combining) cycles
Dynamic deferred transaction support
Sleep mode support
System management interrupt, memory remap and STPCLK mechanism
• Concurrent PCI Bus controller
PCI bus are synchronous / pseudo-synchronous to host CPU bus
33 MHz operation on the primary PCI bus
PCI-to-PCI bridge configuration on the 66MHz PCI bus
Peer concurrency
Concurrent multiple PCI master transactions
Zero wait state PCI master and slave burst transfer rate
PCI to system memory data streaming up to 132MB/s
PCI master snoop ahead and snoop filtering
Two lines of CPU to PCI posted write buffers
Byte merging in the write buggers to reduce the number of PCI cycles and to
create further PCI bursting possibilities
Enhanced PCI command optimization
48 levels of post write buffers from PCI masters to DRAM
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