Cypress CY8CKIT-059 PSoC 5LP Prototyping Kit - Target PSoC 5 LP Board

CY8CKIT-059 PSoC® 5LP Prototyping Kit Guide, Doc. #: 001-96498 Rev. *G 21
Hardware
4.2 Hardware Details
4.2.1 Target Board
The target board uses the PSoC 5LP family device. PSoC 5LP is the industry's most integrated
programmable SoC, integrating high-precision and programmable analog and digital peripherals,
and an Arm
®
Cortex™-M3 CPU. The PSoC 5LP features a high-precision analog-to-digital converter
(ADC), programmable amplifiers, flexible digital subsystem, unmatched parallel co-processing digital
filter block (DFB), high-throughput peripherals such as DMA, CAN, and USB, and standard
communication and timing peripherals. The programmable analog and digital subsystems allow
flexibility and in-field tuning of the design. For more information, refer to the PSoC 5LP family
datasheet in the PSoC 5LP web page.
Figure 4-2. Schematic of PSoC 5LP (Target)
VDDD
P1_1PROG_SWDCLK
P1_0PROG_SWDIO
P_SWO P1_3
P_TDI P1_4
VSSA
PROG_RESET
XRES
VDDA
DM_P
DP_P
P0_0
P0_1
P12_0
P12_1
P12_6
VDDIO2
P12_7
P2_6
P2_7
P12_4
P1_2
P3_7
P3_6
P3_0 P3_4 P3_5 P1_7 P1_6 P3_1
VDDD
P12_5
P2_5
P1_5
P2_0 P2_4 P2_3 P2_2 P2_1 P15_5 P15_4
P15_3
P15_2
P0_5
P15_0 P15_1 P3_2
VSSD
P_VCCD
VSSD P_VCCD
P3_3
VSSD
VDDIO1 VDDIO3
P0_6 P0_7 P0_4
P12_2
P12_3
VDDIO0
P0_3
P0_2
VCCA
VSSD
DP
DM
U2
CY8C5888LTI-LP097 QFN68
P2_6
1
P2_7
2
P12_4 I2C0_SCL, SIO
3
P12_5 I2C0_SDA, SIO
4
VSSB
5
IND
6
VBOOST
7
VBAT
8
VSSD
9
XRES
10
P1_0
11
P1_1
12
P1_2
13
P1_3
14
P1_4
15
P1_5
16
VDDIO1
17
P1_6
18
P1_7
19
P12_6_SIO
20
P12_7_SIO
21
P15_6 DP
22
P15_7 DM
23
VDDD
24
VSSD
25
VCCD
26
P15_0
27
P15_1
28
P3_0
29
P3_1
30
P3_2
31
P3_3
32
P3_4
33
P3_5
34
VDDIO3
35
VDDIO0
52
P0_3
51
P0_2
50
P0_1
49
P0_0
48
SIO_P12_3
47
SIO_P12_2
46
VSSD
45
VDDA
44
VSSA
43
VCCA
42
P15_3
41
P15_2
40
SIO, I2C1_SDA P12_1
39
SIO, I2C1_SCL P12_0
38
P3_7
37
P3_6
36
P2_4
66
P2_3
65
P2_2
64
P2_1
63
P2_0
62
P15_5
61
P15_4
60
VDDD
59
VSSD
58
VCCD
57
P0_7
56
P0_6
55
P0_5
54
P0_4
53
VDDIO2
67
P2_5
68
EPAD
69
0603
R16 22E
0603
R17 22E