Application Note 25 of 42 001-65209 Rev.*I
2021-03-19
Getting Started with FX2LP™
5.4 GPIF Designer
The bulkloop example handles everything on-chip, where the 8051 checks flags, moves bytes between endpoint
FIFOs, and updates the development kit status indicators (LEDs and 7-segment readout). Most FX2LP designs
do more than this, transporting data between FX2LP and outside peripherals, such as disk drives or image
sensors. For this purpose, the GPIF provides a fast and flexible interface to outside systems. This section
highlights AN66806 - Getting Started with EZ-USB FX2LP GPIF, which gives step-by-step instructions for
using the Cypress GPIF Designer tool.
The first step in a GPIF design is to fill in a block diagram with the interface signals, as Figure 26 shows.
Figure 26 GPIF Designer Block Diagram Tab
The GPIF has six Control (CTL) outputs and six Ready (RDY) inputs that you can rename in the block diagram by
right-clicking in the RDY or CTL text blocks. Your names propagate through GPIF Designer, appearing as choices
for state machine decision points and waveform names.
Figure 27 GPIF Waveform Entry Creates States
Figure 27 shows a GPIF Designer waveform entry screen. In this simple example, the internal 48-MHz clock is
divided by 2 and 4, and output on the renamed CTL0 (CLKby2) and CTL1 (CLKby4) pins. The vertical dotted lines
show the clock edges on which transitions can occur; these can be set to rising or falling edges. To create a
transition, you click in the desired waveform on a clock edge. This toggles the waveform and inserts a red
triangle to mark the transition point. You can delete these triangles or drag them to different clock edges, and
set logic levels directly to 1 or 0 with mouse clicks.
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