Cypress EZ-USB CX3 - User Manual

EZ-USB
®
CX3 Technical Reference Manual
(Supplement to the EZ-USB FX3 Technical Reference Manual)
Doc. No. 001-91492 Rev. *B

Cypress EZ-USB CX3 Specifications

General

Brand	Cypress
Model	EZ-USB CX3
Category	Controller
Language	English

Summary

1.1 Introduction

1.2 CX3 Features

1.3 Block Diagram

1.4 MIPI CSI-2 Block Configuration APIs

1.5 MIPI CSI-2 Block

1.6 CX3 MIPI CSI-2 Stream Formats

1.7 MIPI CSI-2 Block Clocks

1.7.1 Reference Clock (REFCLK)

Input clock for the MIPI CSI-2 block, must be between 6 and 40 MHz.

1.7.2 PLL Clock (PLL_CLK)

Primary clock for MIPI CSI-2 block, derived from reference clock.

1.7.3 CSI RX LP ↔ HS Clock

Clock for detecting CSI Link Low Power/High Speed transitions.

1.7.4 Output Parallel Clock (PCLK)

Clock driving the fixed-function GPIF II interface, derived from PLL_CLK.

1.7.5 Image Sensor Reference Clock (MCLK)

Optional clock output for image sensor, sourced from PLL_CLK.

1.8 CX3 MIPI CSI-2 Block Power Modes

1.9 Fixed-Function GPIF II Interface on CX3

1.10 MIPI CSI-2 Block Registers

1.10.1 CX3_SYSTEM_CTRL (Register Address: 0 x0002)

Controls Sleep and Software Reset functionality for the MIPI CSI-2 block.

1.10.2 CX3_CONFIG_CTRL (Register Address: 0 x0004)

Controls data lanes and output data mode for the MIPI CSI-2 block.

1.10.3 CX3_FIFO_CTRL (Register Address: 0 x0006)

Determines FIFO trigger level for parallel data output to GPIF II.

1.10.4 CX3_DATA_FMT (Register Address: 0 x0008)

Controls the output data format for the MIPI CSI-2 block.

1.10.5 CX3_MCLK_CTRL (Register Address: 0 x000 C)

Configures MCLK divider and controls Image Sensor Reference Clock output.

1.10.6 CX3_CSI_SENSOR_SIG_EN (Register Address: 0 x0010)

Enables/disables XSHUTDOWN and XRESET signals from MIPI CSI-2 block.

1.10.7 CX3_CSI_SENSOR_SIG_VAL (Register Address: 0 x0014)

Configures drive value for XSHUTDOWN and XRESET signals.

1.10.8 CX3_PLL_CTRL0 (Register Address: 0 x0016)

Configures the PLL clock on the MIPI CSI-2 block.

1.10.9 CX3_PLL_CTRL1 (Register Address: 0 x0018)

Configures PLL clock frequency range and enable settings.

1.10.10 CX3_CLK_CTRL (Register Address: 0 x0020)

Configures interface clock dividers for the MIPI CSI-2 block.

1.10.11 CX3_BYTE_COUNT (Register Address: 0 x0022)

Configures byte count per active line for the MIPI CSI-2 block.

1.10.12 CX3_PHY_TIME_DELAY (Register Address: 0 x0060)

Configures delay parameters for the MIPI CSI-2 Receiver PHY.

1.11 CX3 MIPI CSI-2 APIs

1.11.1 CyU3 PMipicsilnit()

Initializes the MIPI CSI-2 block on the CX3 device.

1.11.2 CyU3 PMipicsiDeInit()

De-initializes the MIPI-CSI interface block on the CX3 device.

1.11.3 CyU3 PMipicsiReset()

Resets the MIPI-CSI block on the CX3, supporting hard and soft resets.

1.11.4 CyU3 PCx3 DeviceReset()

Resets the CX3 device and the image sensor using MIPI XRESET.

1.11.5 CyU3 PMipicsiSleep()

Disables PLL clocks and places the MIPI CSI-2 block in low-power sleep.

1.11.6 CyU3 PMipicsiWakeup()

Enables clocks to take MIPI CSI-2 block from low power sleep to Active.

1.11.7 CyU3 PMipicsiSetSensorControl()

Drives XRES and XSHUTDOWN signals from CX3 to Image sensor.

1.11.8 CyU3 PMipicsiCheckBlockActive()

Checks if the MIPI CSI-2 block is Active or in low power sleep.

1.11.9 CyU3 PMipicsiSetIntfParams()

Configures MIPI CSI-2 block parameters over the I2C interface.

1.11.10 CyU3 PMipicsiQueryIntfParams()

Reads back MIPI-CSI interface parameters from the block.

1.11.11 CyU3 PMipicsiGetErrors()

Gets counts of CSI-2 protocol and physical layer errors.

1.11.12 CyU3 PMipicsiGpifLoad()

Selects GPIF data bus-width and DMA buffer size.

1.12 Additional References

1.13 Glossary