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General| Brand | Cypress |
|---|---|
| Model | EZ-USB FX3 |
| Category | Controller |
| Language | English |
Overview of USB 3.0 and its changes from USB 2.0, including power management.
Lists key features of FX3 and FX3S, including USB, GPIF II, CPU, and connectivity.
Describes the functional blocks: CPU, DMA, USB, GPIF II, serial peripherals, and storage.
Details features of the ARM9 core, including frequency, instruction support, caches, TCM, and debug interface.
Explains the ARM9 core, its interfaces, and the interrupt controller's role.
Details system memory, TCM, DMA bandwidth, MMIO access, and latency guarantees.
Covers memory regions, system interconnect, low-power operations, cache operations, and memory usage.
Explains GPIO pin functionality, multiplexing, simple vs. complex GPIOs, and I/O matrix configuration.
Describes how peripheral clocks are configured using GCTL registers and clock sources.
Details power domains, power modes (normal, suspend, standby, core power down), and wakeup sources.
Introduces the FX3 DMA controller, its distributed nature, and AHB interconnect usage.
Outlines DMA features including distributed controllers, transfer support, gateways, and adapters.
Provides an overview of the DMA adapter architecture and its role in peripheral communication.
Explains clocking and the distributed DMA controllers architecture.
Introduces USB as a peripheral interconnect, its speeds, and evolution to USB 3.0.
Lists USB controllers supported by FX3, including UIB, USB 3.0/2.0 controllers, and OTG.
Details the USB interface block, controllers, I/O system, and operational modes.
Explains the USB 3.0 function controller's role in link and protocol layers.
Covers FX3's capability to support USB 2.0 host, peripheral, and OTG controller functions.
Explains the two dedicated DMA adapters managing USB data flow and their mapping to sockets.
Describes how FX3 firmware manages USB 3.0 and USB 2.0 PHY operations for host connection negotiation.
Details how to program USB functions, including initialization and enabling.
Provides a code example for the UIB initialization sequence for the USB 3.0 function.
Implements the sequence to enable the USB 3.0 function controller.
Explains the fallback mechanism when USB 3.0 termination or link training fails.
Summarizes GPIF II features like master/slave operation, programmable states, data bus width, and interface frequency.
Explains GPIF II state machine configuration, state properties, triggers, and actions.
Details the various actions that can be programmed within a GPIF II state machine for data transfer and control.
Describes triggers that cause state transitions, including external and internal signals.
Introduces the GUI tool for developing GPIF II state machines and generating configuration files.
Guides on configuring the GPIF II outside-world interface using the Interface Definition tab.
Guides on implementing GPIF II state machines using the designer tool.
Describes how to add states to the state machine canvas using the right-click menu.
Explains how to add actions to a selected state from the Action List window.
Details how to draw transitions between states by dragging the mouse cursor.
Guides on opening the Transition Equation Entry dialog and defining logical functions for state transitions.
Explains how to set state properties like name, repeat count, and associated actions.
Describes how to simulate relative timing of input/output signals using the Timing window.
Discusses limitations like binary state machines and transition equation complexity, and techniques to overcome them.
Lists I2C features such as master mode, clock speeds, addressing, and transfer modes.
Explains I2C operations on FX3, including reset, initialization, and data transfer methods.
Lists SPI features like master mode, transfer modes, data unit length, and boot options.
Explains SPI operations on FX3, including reset, initialization, and transfer modes.
Provides example code for SPI register-based and DMA-based transfers using FX3 SDK APIs.
Lists UART features like baud rate, modes, communication type, oversampling, and flow control.
Explains UART operations on FX3, including reset, initialization, and programming models.
Lists I2S features like transmitter function, sampling frequencies, and data value formats.
Explains the I2S bus for digital audio communication, clock/data separation, and interface pins.
Details I2S operations on FX3, including programming model and transfer types.
Lists GPIO features like pin configuration, complex GPIOs, drive strength, and pull-up/pull-down.
Describes general-purpose I/O pins, multiplexing, and their use as simple or complex GPIOs.
Explains GPIO operations including reset and initialization.
Provides example code for configuring GPIO pins as input, output, or for PWM generation.
Introduces the chapter on FX3 registers and provides an overview of the memory map.
Explains the format used for register descriptions, including name, bits, accessibility, and default values.
Describes the VIC IRQ Status Register, which shows IRQ status after masking.
Covers the VIC Interrupt Select register for designating lines as FIQ or IRQ.
Describes the VIC Interrupt Enable Register for enabling interrupts at specific bit positions.
Details the VIC Interrupt Clear Register for disabling and masking interrupts.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Configures GPIO pins for simple functionality, overriding default functions.
Configures GPIO pins for complex functionality, including timer/counter capabilities.
Defines pull-up and pull-down drive strength capability for I/O pins.
Configures internal weak pull-up resistors for I/O pins.
Configures internal weak pull-down resistors for I/O pins.
Allows firmware to monitor power status of various I/O blocks.
Configures CPU and bus clock dividers based on clock source.
Configures GPIO fast clock divider and source.
Configures the divider for the I2C clock block.
Configures the core clock provided to the UART peripheral.
Configures the I2S core clock.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates the polarity for wakeup detect signals.
Indicates which wakeup source caused the system wakeup.
Controls watchdog timers, including mode, interrupt, and reset.
Introduces the FX3 DMA controller, its distributed nature, and AHB interconnect usage.
Outlines DMA features including distributed controllers, transfer support, gateways, and adapters.
Provides an overview of the DMA adapter architecture and its role in peripheral communication.
Explains clocking and the distributed DMA controllers architecture.
Introduces USB as a peripheral interconnect, its speeds, and evolution to USB 3.0.
Lists USB controllers supported by FX3, including UIB, USB 3.0/2.0 controllers, and OTG.
Details the USB interface block, controllers, I/O system, and operational modes.
Explains the USB 3.0 function controller's role in link and protocol layers.
Covers FX3's capability to support USB 2.0 host, peripheral, and OTG controller functions.
Explains the two dedicated DMA adapters managing USB data flow and their mapping to sockets.
Describes how FX3 firmware manages USB 3.0 and USB 2.0 PHY operations for host connection negotiation.
Details how to program USB functions, including initialization and enabling.
Provides a code example for the UIB initialization sequence for the USB 3.0 function.
Implements the sequence to enable the USB 3.0 function controller.
Explains the fallback mechanism when USB 3.0 termination or link training fails.
Summarizes GPIF II features like master/slave operation, programmable states, data bus width, and interface frequency.
Explains GPIF II state machine configuration, state properties, triggers, and actions.
Details the various actions that can be programmed within a GPIF II state machine for data transfer and control.
Describes triggers that cause state transitions, including external and internal signals.
Introduces the GUI tool for developing GPIF II state machines and generating configuration files.
Guides on configuring the GPIF II outside-world interface using the Interface Definition tab.
Guides on implementing GPIF II state machines using the designer tool.
Describes how to add states to the state machine canvas using the right-click menu.
Explains how to add actions to a selected state from the Action List window.
Details how to draw transitions between states by dragging the mouse cursor.
Guides on opening the Transition Equation Entry dialog and defining logical functions for state transitions.
Explains how to set state properties like name, repeat count, and associated actions.
Describes how to simulate relative timing of input/output signals using the Timing window.
Discusses limitations like binary state machines and transition equation complexity, and techniques to overcome them.
Lists I2C features such as master mode, clock speeds, addressing, and transfer modes.
Explains I2C operations on FX3, including reset, initialization, and data transfer methods.
Lists SPI features like master mode, transfer modes, data unit length, and boot options.
Explains SPI operations on FX3, including reset, initialization, and transfer modes.
Provides example code for SPI register-based and DMA-based transfers using FX3 SDK APIs.
Lists UART features like baud rate, modes, communication type, oversampling, and flow control.
Explains UART operations on FX3, including reset, initialization, and programming models.
Lists I2S features like transmitter function, sampling frequencies, and data value formats.
Explains the I2S bus for digital audio communication, clock/data separation, and interface pins.
Details I2S operations on FX3, including programming model and transfer types.
Lists GPIO features like pin configuration, complex GPIOs, drive strength, and pull-up/pull-down.
Describes general-purpose I/O pins, multiplexing, and their use as simple or complex GPIOs.
Explains GPIO operations including reset and initialization.
Provides example code for configuring GPIO pins as input, output, or for PWM generation.
Introduces the chapter on FX3 registers and provides an overview of the memory map.
Explains the format used for register descriptions, including name, bits, accessibility, and default values.
Describes the VIC IRQ Status Register, which shows IRQ status after masking.
Covers the VIC Interrupt Select register for designating lines as FIQ or IRQ.
Describes the VIC Interrupt Enable Register for enabling interrupts at specific bit positions.
Details the VIC Interrupt Clear Register for disabling and masking interrupts.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Configures GPIO pins for simple functionality, overriding default functions.
Configures GPIO pins for complex functionality, including timer/counter capabilities.
Defines pull-up and pull-down drive strength capability for I/O pins.
Configures internal weak pull-up resistors for I/O pins.
Configures internal weak pull-down resistors for I/O pins.
Allows firmware to monitor power status of various I/O blocks.
Configures CPU and bus clock dividers based on clock source.
Configures GPIO fast clock divider and source.
Configures the divider for the I2C clock block.
Configures the core clock provided to the UART peripheral.
Configures the I2S core clock.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates the polarity for wakeup detect signals.
Indicates which wakeup source caused the system wakeup.
Controls watchdog timers, including mode, interrupt, and reset.
Lists Storage Interface Block features for SD/MMC/SDIO, including ports and bus widths.
Shows the block diagram of the SIB connecting storage devices to the processor and other peripherals.
Details the SD bus signals, CMD, DAT, and power signals.
Details the SD bus signals, CMD, DAT, and power signals.
Explains SDIO card as an extension of SD specification for I/O functions.
Covers S-port operations, initialization, and housekeeping performed by the storage driver.
Guides on configuring the S-port I/O matrix and setting interface parameters like voltage and DDR.
Explains how to perform SD/MMC read/write operations using DMA transfers.
Details configuration and initialization for SDIO cards, including IO_RW_DIRECT command.
Introduces the chapter on FX3 registers and provides an overview of the memory map.
Explains the format used for register descriptions, including name, bits, accessibility, and default values.
Describes the VIC IRQ Status Register, which shows IRQ status after masking.
Covers the VIC Interrupt Select register for designating lines as FIQ or IRQ.
Describes the VIC Interrupt Enable Register for enabling interrupts at specific bit positions.
Details the VIC Interrupt Clear Register for disabling and masking interrupts.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Configures GPIO pins for simple functionality, overriding default functions.
Configures GPIO pins for complex functionality, including timer/counter capabilities.
Defines pull-up and pull-down drive strength capability for I/O pins.
Configures internal weak pull-up resistors for I/O pins.
Configures internal weak pull-down resistors for I/O pins.
Allows firmware to monitor power status of various I/O blocks.
Configures CPU and bus clock dividers based on clock source.
Configures GPIO fast clock divider and source.
Configures the divider for the I2C clock block.
Configures the core clock provided to the UART peripheral.
Configures the I2S core clock.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates the polarity for wakeup detect signals.
Indicates which wakeup source caused the system wakeup.
Controls watchdog timers, including mode, interrupt, and reset.
Lists Storage Interface Block features for SD/MMC/SDIO, including ports and bus widths.
Shows the block diagram of the SIB connecting storage devices to the processor and other peripherals.
Details the SD bus signals, CMD, DAT, and power signals.
Details the SD bus signals, CMD, DAT, and power signals.
Explains SDIO card as an extension of SD specification for I/O functions.
Covers S-port operations, initialization, and housekeeping performed by the storage driver.
Guides on configuring the S-port I/O matrix and setting interface parameters like voltage and DDR.
Explains how to perform SD/MMC read/write operations using DMA transfers.
Details configuration and initialization for SDIO cards, including IO_RW_DIRECT command.
Introduces the chapter on FX3 registers and provides an overview of the memory map.
Explains the format used for register descriptions, including name, bits, accessibility, and default values.
Describes the VIC IRQ Status Register, which shows IRQ status after masking.
Covers the VIC Interrupt Select register for designating lines as FIQ or IRQ.
Describes the VIC Interrupt Enable Register for enabling interrupts at specific bit positions.
Details the VIC Interrupt Clear Register for disabling and masking interrupts.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Defines port usage and implementation for GPIO pins, requiring configuration before accessing alternate functions.
Configures GPIO pins for simple functionality, overriding default functions.
Configures GPIO pins for complex functionality, including timer/counter capabilities.
Defines pull-up and pull-down drive strength capability for I/O pins.
Configures internal weak pull-up resistors for I/O pins.
Configures internal weak pull-down resistors for I/O pins.
Allows firmware to monitor power status of various I/O blocks.
Configures CPU and bus clock dividers based on clock source.
Configures GPIO fast clock divider and source.
Configures the divider for the I2C clock block.
Configures the core clock provided to the UART peripheral.
Configures the I2S core clock.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates which wakeup sources are enabled to wake up the system from suspend/standby modes.
Indicates the polarity for wakeup detect signals.
Indicates which wakeup source caused the system wakeup.
Controls watchdog timers, including mode, interrupt, and reset.
Identifies the block and controls its power/clock/reset state. These registers are located in the CPU/Interconnect power and clock domains.
Controls the block's power/clock/reset state. These registers are located in the CPU/Interconnect power and clock domains.
Lists I2S features like transmitter function, sampling frequencies, and data value formats.
Explains the I2S bus for digital audio communication, clock/data separation, and interface pins.
Details I2S operations on FX3, including programming model and transfer types.
Initializes the FX3 I2S block to operate at the default sampling rate of 8 kHz.
Configures the FX3 I2S block, setting the interface sampling frequency and word width.
Shows how to transfer data from USB endpoints to I2S channels using DMA.
Lists I2C features such as master mode, clock speeds, addressing, and transfer modes.
Explains I2C operations on FX3, including reset, initialization, and data transfer methods.
Details I2C core reset, enablement, clock speed configuration, and power control.
Explains how data is transferred using I2C, including register and DMA paths.
Details register usage for I2C transfers, including preamble, command, and data registers.
Explains DMA-based transfers using I2C sockets and the initiation process.
Outlines the steps to select DMA mode, enable the block, and program the byte count.
Provides example code for register-based and DMA-based I2C transfers using FX3 SDK APIs.
Defines UART configuration options like enable, clear FIFO, and various modes.
Explains UART operations on FX3, including reset, initialization, and programming models.
Explains register usage for conveying core data and interrupts.
Provides example code for UART initialization and message transfer/reception.
Lists SPI features like master mode, transfer modes, data unit length, and boot options.
Explains the SPI bus as a synchronous serial data link, master/slave modes, and pin functions.
Explains SPI operations on FX3, including reset, initialization, and transfer modes.
Explains register-based and DMA-based SPI transfers, data paths, and endianness configuration.
Provides example code for SPI register-based and DMA-based transfers using FX3 SDK APIs.
Lists GPIO features like pin configuration, complex GPIOs, drive strength, and pull-up/pull-down.
Describes general-purpose I/O pins, multiplexing, and their use as simple or complex GPIOs.
Explains GPIO operations including reset and initialization.
Provides example code for configuring GPIO pins as input, output, or for PWM generation.
Describes the descriptor chain pointer register for sockets.
Defines the transfer size register for sockets.
Stores the transfer count for sockets.
Provides the status and interrupt control bits for sockets.
Details the socket interrupt request bits.
Masks socket interrupt requests to control reporting to the CPU.
Defines the descriptor buffer base address register.
Provides descriptor synchronization pointers.
Manages descriptor chain pointers for producer and consumer.
Configures descriptor size, including byte count, buffer size, and status bits.
Facilitates event communication between sockets for DMA operations.
Contains interrupt request bits for each socket, logically OR'd.
Provides global status for the DMA adapter, including word size and queue size.
Identifies the Storage Interface Block IP with version and block ID.
Controls power, clock, and reset state for the storage interface block.
Specifies the command index for SD/MMC/SDIO commands.
Holds the lower 32 bits of the SD/MMC/SDIO command argument.
Holds the upper 32 bits of the SD/MMC/SDIO command argument.
Captures the first eight bits of the response from the card.
Holds response data received from the card for command response.
Holds response data received from the card for command response.
Holds response data received from the card for command response.
Holds response data received from the card for command response.
Holds response data received from the card for command response.
Specifies the length and format of the command and response.
Holds the number of data blocks to be completed during the ongoing SD/MMC command transfer.
Holds the block length for transfer. The CRC is computed on this block length.
Configures clock, signaling, and so on for each of the storage ports.
Holds configuration parameters that affect SD/MMC data transfers.
Initiates SD/MMC/SDIO commands and data transfers.
Reflects the current status of the SIB state machines.
Displays interrupt status bits.
Controls whether interrupt status should trigger an interrupt to the CPU.
Controls timing between command and response.
Controls the timing between multiple commands.
Controls the timeout period for data read operations.
Provides a mechanism to reset eMMC devices.
Configures the DLL phases and enables the DLL.
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