EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 47
Memory and System Interconnect
â– MMIO-The register space that holds all the configuration and status registers implemented by all the blocks on the FX3
device. While a total memory region of 256 MB has been allocated for the registers, most of this memory is unused and
unimplemented. Refer to the chapters on each of the FX3 hardware blocks for information on the registers corresponding
to those blocks.
â– BootROM-A 32 KB ROM region that is preprogrammed with the FX3 device bootloader. The bootloader implements mul-
tiple boot modes such as USB boot, I2C boot, SPI boot, and GPIF boot. The desired boot mode is selected through a set
of pin straps. This memory region is not accessible to FX3 user applications.
â– VIC-Control and status registers for the VIC block. They are separate from the other MMIO registers and are located at
the address 0xFFFFF000.
3.3.2 System Interconnect
The FX3 device implements a hierarchical AHB-based interconnect system that allows the device interfaces and the ARM
CPU to access the system memory with high throughput and bounded latency. Different parts of the FX3 device function at
different clock rates. The ARM CPU typically runs on a 200 MHz clock and has separate 32-bit wide buses for instruction and
data access. The DMA interconnect runs at 100 MHz and has separate 64-bit buses for read and write accesses. The MMIO
interconnect runs at 100 MHz and has a single 32-bit bus for all register accesses. The system RAM is organized as 128-bit
wide memories and is clocked at 200 MHz.
As the DMA interconnect provides separate buses for read and write transfers, it can issue one read access and one write
access during each DMA clock cycle. This means that the DMA interconnect can simultaneously support DMA read and DMA
write traffic at 800 MBps each (100 MHz times 8 bytes in the 64-bit bus equals 800 MBps).
The system interconnect supports the following kinds of transfers:
â– CPU traffic to system RAM
â– DMA traffic to system RAM
â– CPU accesses to MMIO registers
â– DMA accesses to MMIO registers
Note: DMA access to MMIO registers is used to synchronize data transfers between a pair of communicating hardware
blocks.
A specialized FX3 memory controller arbitrates between all these accesses. The memory controller connects to the high-
speed system interconnect, which has two 128-bit wide buses running at 200 MHz. The memory controller guarantees equal
SRAM bandwidth for CPU and DMA accesses. It also allows the DMA controller to use any unused CPU cycles so that typical
FX3 applications can sustain a higher bandwidth.
3.3.3 Low-Power Operations
FX3 supports low-power operating modes in which the device clocks can be turned off and most of the blocks can be
powered off. Ta b l e 3- 1 shows the state of various FX3 blocks in the different power modes.
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