Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 168
Low Performance Peripherals (LPP)
Figure 8-1. LLP's Interfaces and DMA Fabric
Upon reset, all the LPP blocks are disabled. All the LPP blocks become operational only after an enable bit in a configuration
register is set. Each block has its own block-level soft reset; LPP soft reset and the global reset are synchronized to the core
clock. All the resets need to be deasserted for the block to be operational.
8.1 I2C Interface
8.1.1 I2C Block Features
The I2C block offers the following features:
■ Operates in master mode
UART Egress Socket
UART Ingress Socket
UART
8 4
UART
DMA
Thread
I2S Right Egress
Socket
I2S Left Egress
Socket
I2S transmitter
8
4
I2S Right
DMA
Thread
SPI Egress Socket
SPI Ingress Socket
SPI Master
Transciever
8 4
SPI DMA
Thread
I2C Egress Socket
I2C Ingress Socket
I2C
Multi-Master
Trasciever
8 2
I2C DMA
Thread
MMIO Registers
8
I2S Left DMA
Thread
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IO Mux
DMA FabricMMIO Fabric

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English