EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 135
General Programmable Interface II (GPIF II)
7.4.5.2 Counters
GPIF II has three counters for control, address, and data. The reset value and count limit value can be programmed for each
counter. The counter value is incremented by using the actions provided in the GPIF II Designer tool. A counter reaching its
programmed limit provides one of the available GPIF II trigger signals.
7.4.5.3 GPIF II Interrupt
Any GPIF II state can interrupt the CPU by asserting the INTR_CPU action provided in the GPIF II Designer tool. GPIF II state
machine execution continues after interrupting the CPU.
7.4.6 Threads and Sockets
A thread in the GPIF II context is a physical, hardware, data channel. There are four physical threads, each with an
independent controller. A socket, on the other hand, is very similar to an endpoint in the USB context. Each socket has buffers
assigned to it during initialization. A particular thread is mapped to a particular socket during initialization. This mapping can
be changed later during execution. A GPIF II thread is basically a pipe through which the data on the GPIF II interface is
connected to the socket (and hence buffer), where it is required to be written to or read from. Though there are four
independent threads, GPIF II can access only one of them at a time. Which thread is to be accessed can be specified using
the address bus on the GPIF II interface (two address bits select one of the four threads).
7.4.6.1 Difference Between PP_MODE=0 and PP_MODE=1
PP_MODE is a bit field of GPIF II Configuration register (GPIF_CONFIG). This decides the two modes of GPIF II. One mode,
PP_MODE=0, is designed for peripherals that use hardware signaling to switch end points or sockets. In this mode, the 32
sockets are mapped to 4 threads in a modulo-4 fashion. The other mode, called PP_MODE=1, is designed for interfacing with
chips that have DMA engines that transfer large data and switch end points through the accessing processor port (PP)
registers. In this mode, all the sockets are connected to a single thread inside the GPIF II.
PP_MODE=0 enables all four threads described in the previous section, as shown in Figure 7-18.
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