Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 206
Storage Ports
9.5.1.4 Setting the S-Port Clock
The S0/S1 interface clock is enabled or disabled by the bit SDMMC_CLK_DIS in the register SDMMC_CS (SD/MMC/SDIO
card command and status register). For bit definitions, refer to SDMMC_CS register on page 647.
The clock values are set using the register GCTL_SIB0_CORE_CLK and GCTL_SIB1_CORE_CLK (SIB Port 0/1 core clock
configuration register). GCTL_SIBx_CORE_CLK.DIV determines the clock divider value for dividing the PLL system clock.
GCTL_SIBx_CORE_CLK.SRC selects the clock source, and GCTL_SIBx_CORE_CLK.EN enables it.
The clock choice for the divisor is user-configurable. For example, the following frequencies can be configured through these
registers:
■ 400 kHz: For the SD/MMC card initialization
■ 20 MHz: For a card with 0- to 20-MHz frequency
■ 24 MHz: For a card with 0- to 26-MHz frequency
■ 48 MHz: For a card with 0- to 52-MHz frequency (48-MHz frequency on SD_CLK is supported when the clock input to
FX3S is 19.2 MHz or 38.4 MHz.)
■ 52 MHz: For a card with 0- to 52-MHz frequency (52-MHz frequency on SD_CLK is supported when the clock input to
FX3S is 26 MHz or 52 MHz)
■ 100 MHz: For a card with 0- to 100-MHz frequency
If the DDR mode is selected, data is clocked on both the rising and falling edge of the SD clock. DDR clocks run up to
52 MHz.
9.5.1.4.1 Powering On the SIB
The SIB block is power cycled using the SIB_POWER.RESETN bit and then polled for the SIB_POWER.ACTIVE bit, which
remains deasserted until initialization is complete. SIB_POWER.ACTIVE = 1 indicates block is initialized and ready for
operation. For bit definitions, refer to SIB_POWER register on page 631.
9.5.1.4.2 Initializing SIB Sockets
Initially, all sockets are disabled, and socket interrupts are cleared using the registers SCK_STATUS, SCK_INTR and
SCK_INTR_MASK. Refer to 5.5.5 Sockets on page 65 for more details on sockets.
Later, the active SIB socket number for read/write is set using SDMMC_CS.SOCKET before initiating reads/writes from/to the
SD/MMC/SDIO device.
9.5.1.4.3 S-Port I/O Drive Strength
The S-port I/O drive strength is programmable similar to any other I/O pin as discussed in 4.1.2 I/O Drive Strength on
page 53.
9.5.1.5 Sending SD/MMC/SDIO Commands
The SD/SDIO/MMC command to be sent on the command bus is specified through the register SDMMC_CMD_IDX. The cmd
field specifies the command index that is to be included in the command sent. When the command is sent, the hardware
sends out start and transmission bits followed by (SDMMC_CMD_RESP_FMT.CMDFRMT+1 bits) a 7-bit CRC code and an
end bit. The (SDMMC_CMD_RESP_FMT.CMDFRMT+1) bits include as many bits as necessary in the following order:
command index (6 bits), argument (starting from bit 31 of SDMMC_CMD_ARG0), SDMMC_CMD_ARG1. The
SDMMC_CMD_ARG0 register holds the 32-bit SD/MMC/SDIO command argument. Any additional argument bits for the
expanded command may be placed in the SDMMC_CMD_ARG1 register. There is no need for the software to specify start,
transmission and end bits-they are to be generated by the hardware.
For bit definitions, refer to SDMMC_CMD_IDX register on page 632, SDMMC_CMD_RESP_FMT register on page 641,
SDMMC_CMD_ARG0 register on page 633 and SDMMC_CMD_ARG1 register on page 634.

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English