Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 84
Universal Serial Bus (USB)
Table 6-2. USB Global Interrupt Sources to VIC
UIB has a global interrupt register, UIB_INTR, which contains interrupt sources from the respective functional blocks (USB
3.0 function, USB 2.0 function, USB 2.0 host, USB 2.0 OTG, charger detect, EPM). The UIB core interrupt to VIC is the logical
OR of interrupt sources in UIB_INTR.
The USB 3.0 link layer interrupts are located in UIB_LNK_INTR. UIB_INTR.LNK_INT is the logical OR of the interrupt sources
in UIB_LNK_INTR.
USB 3.0 protocol layer interrupts are located in UIB_PROT_INTR. UIB_INTR.PROT_INT is the logical OR of the interrupt
sources in UIB_PROT_INTR.
USB 3.0 function endpoint interrupts are located in UIB_PROT_EP_INTR. UIB_INTR.PROT_EP_INT is the logical OR of the
interrupt sources in UIB_PROT_EP_INTR.
6.6.1.3 USB 3.0 Functional Description
The SuperSpeed bus is a layered communications architecture that comprises the following elements:
SuperSpeed interconnect: The SuperSpeed interconnect is the manner in which devices are connected to and communicate
with the host over the SuperSpeed bus. It includes the topology of devices connected to the bus, the communication layers,
the relationships between them, and how they interact to accomplish information exchanges between the host and devices.
Devices: Devices implement the required function end of SuperSpeed communication layers to provide a specific function of
the application, for example, a mass storage device. The terms "USB device" and "USB function" are interchangeable.
Host: The host implements the required host end of SuperSpeed communication layers to use the functions of the attached
devices. It owns the SuperSpeed data activity schedule and management of the SuperSpeed bus and all devices connected
to it.
As shown in Figure 6-2, the rows (device or host, protocol, link, physical) represent the communication layers of the
SuperSpeed interconnect, namely:
■ Physical (PHY) layer
■ Link layer
■ Protocol layer
■ The FX3 USB 3.0 function controller design follows the same basic SuperSpeed architecture.
Interrupt VIC Line Interrupt Source Description
usbdma_int 8 UIB DMA sockets UIB DMA interrupt
usbcore_int 9
USB 3.0 function, USB 2.0 function, USB 2.0 host, USB
2.0 OTG, charger detect, EPM
UIB core interrupt
usbep0_int 10 USB 3.0 device or USB 2.0 device EP0 interrupt that is used only in device mode

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English