EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 178
Low Performance Peripherals (LPP)
8.3.5 Data Transfers
The FX3 architecture supports register-based SPI operations for small transfers and DMA-based SPI operations for larger
transfers.
The data from the core side can be received either through the DMA interface or the register interface for transmitting it over
the SPI bus. The registers used on the ARM side to read the data from the core and convey it to the bus are called
EGRESS_DATA registers. The registers used to get the data from the external bus are called INGRESS_DATA registers. The
DMA interface supports sockets that are used for moving the data between the peripheral and the USB 3.0 interconnect. The
sockets used for transmitting the data to the bus are called EGRESS sockets. The DMA sockets that are used for receiving
the data from the bus are called INGRESS sockets.
Apart from the SCK and SSN configurations, SPI endianness also needs to be configured; this can be done by the ENDIAN
bit of the SPI_ CONFIG register.
8.4 Programming Model
SPI is a simple block that does not interpret data. The SPI programming model is similar to I2C except for the control phase.
No control phase is required in SPI, so only the data phase exists.
8.4.1 Register-Based Transfers
4-byte-deep FIFOs hold egress and ingress data in its register space. Based on the status of FIFOs TX_SPACE, TX_HALF,
TX_DONE, and RX_DATA, the RX_HALF flags are asserted in the SPI_STATUS and SPI_INTR registers to indicate to the
firmware.
The firmware can clear the FIFOs by asserting TX_CLEAR and RX_CLEAR from the SPI_CONFIG register. Ta b l e 8- 2 shows
the conditions for the assertion of flags.
Table 8-2. Conditions for Assertion of Flags
8.4.2 DMA-Based Transfers
Ingress and egress sockets can be programmed to interrupt the CPU upon transaction completion. The transceiver always
raises interrupts in error conditions.
There are two separate BYTE_COUNT registers for RX and TX paths. These two registers can be used only for DMA mode
and cannot be used for register mode transfers. The SPI_TX_BYTE_COUNT register specifies the number of bytes to be
written out during DMA transfer. The SPI_RX_BYTE_COUNT register indicates the number of bytes received. Register mode
transfers are always treated as infinite-length transfers.
Once the expected number of data bytes has been received or transmitted (indicated by SPI_TX_BYTE_COUNT or
SPI_RX_BYTE_COUNT), then an end of transfer is indicated to the DMA adapter by setting the RX_DONE or TX_DONE flag
to 1 respectively (of SPI_STATUS and SPI_INTR) in DMA-based transfers.
As SPI protocol is very simple, no special error handling is required apart from handling FIFO overflow and underflow.
FLAG Asserted Egress FIFO State Ingress FIFO State
TX_SPACE Not full -
TX_HALF At least half empty -
TX_DONE Full -
RX_DATA - Not empty
RX_HALF - At least half full
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