EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 144
General Programmable Interface II (GPIF II)
You can opt to have the actions associated with the state repeated until the transition to the next state by selecting the Repeat
actions until next transition option as shown in the figure below.
Figure 7-26. GPIF II Designer (Set State Properties)
7.6.6 Analyzing the Signal Timing of the GPIF II Interface
After entering the state machine corresponding to the P-port interface, you can use the Timing window to simulate the relative
timing of the input and output signals. The GPIF II project should be built without any errors before using the timing window
for simulation.
To perform the timing simulation, select a specific state machine path in the state machine. Save the selected path for further
viewing in a file. You can load a saved timing scenario from the menu provided on the top strip of the Timing window.
You can create a new timing scenario using the Create Scenario dialog box. A toolbar icon to create a scenario appears on
the top strip of the Timing window. You can enter a unique name to identify the scenario being created in the Scenario Name.
Use the Scenario Entry dialog box to select for the simulation a path consisting of a set of states that you can traverse
sequentially.
The Timing window provides the following features:
7.6.6.1 Selection of Time Frame
The display frame of the timing diagram can be selected by specifying the start and end of the time frame. The start and end
of time frame can be specified on the left and right bottom corner of the timing display respectively.
7.6.6.2 Automatic Timing Scale Selection
The timing window will be adjusted to the optimum scale according to the screen resolution and viewable area.
Note The timing simulation is performed based on a model of the GPIF II hardware. The GPIF II hardware execution is
synchronous even if the interface is operating asynchronously. A typical operating (internal) clock frequency of 200 MHz (5-ns
cycle time) is used in the simulation of asynchronous protocols.
7.6.7 Scenario Entry
You can simulate the state machine to view the relative timing and value of the signals in the form of a timing diagram. Select
the state machine path whose behavior is to be simulated.
To Next Page
Loading...
Need help?
General
