EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 112
Universal Serial Bus (USB)
6.9.11.3.1.7 Setup Phase
This EP0 category starts once the scheduler encounters the EP0 in the scheduler memory list for the first time, and the
ep0_code is "11". This category indicates that after the SETUP gets ACKed, the next scheduled EP0 is an IN transaction. The
scheduler informs the TP to issue a SETUP token. If the SETUP token is successful, then the next time the scheduler
encounters the EP0 in the list, it will inform the TP for an EP0-IN transaction. If the SETUP token is not successful, then the
EP0 transaction is terminated and it will retry it the next time it encounters the EP0 in the scheduler memory, as long as the
EP0 is still active and not halted.
6.9.11.3.1.8 Status Phase (IN)
Once a valid EP0 IN ZLP has been received, the scheduler deactivates the EP0 entry if the trns_mode of the scheduler entry
is "0".
6.10 USB OTG Controller
The FX3 USB OTG controller implements the hardware interface between the processor and the USB PHY to allow the
firmware to implement the OTG features. The OTG function requires the firmware implementation to handle the protocol. The
controller hardware generates interrupts on the events, and the firmware handles the event and responds to it as needed.
The FX3 USB OTG controller is compatible with USB OTG 2.0 specifications.
USB OTG defines two protocols: SRP and HNP. SRP is a method for a peripheral to request that the host enable the VBus
bus power. Some hosts may wish to disable the VBus bus power to conserve system power, and this protocol allows
peripherals to connect to the host under such conditions.
The HNP protocol is a method of allowing a peripheral and host to switch roles, with the peripheral serving as the host and the
host receiving commands from the peripheral. For hosts and peripherals, it is necessary to have the D- pull-down resistor
enabled at all times. When a device is acting as a host, it must also enable the D+ pull-down resistor.
6.10.1 Interrupt Requests
USB OTG interrupts are located in UIB_OTG_INTR. UIB_INTR.OTG_INT is the logical OR of the interrupt sources in
UIB_OTG_INTR.
6.10.2 USB OTG Programming Model
FX3 USB OTG controller registers can be accessed directly from the UIB top-level register interface. Following is the list of
these registers.
/* FX3 USB OTG Register Interface */
/* These definitions extracted from the Top Level UIB register interface */
uvint32_t otg_ctrl; /* 0xe003180c */
uvint32_t otg_intr; /* 0xe0031810 */
uvint32_t otg_intr_mask; /* 0xe0031814 */
uvint32_t otg_timer; /* 0xe0031818 */
6.10.2.1 USB OTG Start and Stop
The FX3 OTG controller needs to be initialized before it can handle OTG events. The following code example implements the
OTG controller start and stop sequence.
CyU3PReturnStatus_t
CyU3POtgStart (
CyU3POtgConfig_t *cfg)
{
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