EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 609
SCK_STATUS
0x0C
10.25.4 SCK_STATUS
Socket Status Register
This register contains the status and interrupt control bits. The interrupt request bits are independent of the interrupt mask
bits. The mask bits affect which interrupt request bits are reported to CPU only.
31 GO_ENABLE Indicates whether socket is enabled. When go_enable is cleared while socket is active, ongoing
transfers are aborted after an unspecified amount of time. No update occurs from the descriptor reg-
isters back into memory. When go_enable is changed from 0 to 1, the socket will reload the active
descriptor from memory regardless of the contents of DSCR_ registers. The socket will not wait for an
EVENT to become active if the descriptor is available and ready for transfer (has space or data).
The 'enabled' bit indicates whether the socket is actually enabled or not. This field lags go_enable by
a short but unspecified time.
30 GO_SUSPEND Directs a socket to go into suspend mode when the current descriptor completes. The main use of
this bit is to safely append descriptors to an active socket without actually suspending it (in most
cases). The process looks as follows:
1. GO_SUSPEND=1
2. Modify the chain in memory
3. Check if active descriptor is 0xFFFF or last in chain
4. If so, make corrections as necessary (complicated)
5. Clear any pending suspend interrupts (SCK_INTR[9:5])
6. GO_SUSPEND=0
Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.
continued on next page
SCK_STATUS Socket Status Register 0x0C
b31 b30 b29 b28 b27 b26 b25 b24
GO_ENABLE GO_SUSPEND UNIT WRAPUP SUSP_EOP SUSP_TRANS SUSP_LAST SUSP_PARTIAL
R/W R/W R/W R/W1S R/W R/W R/W R/W
RRRR/W0CRRRR
00000100
SCK_STATUS Socket Status Register
b23 b22 b21 b20 b19 b18 b17 b16
EN_CONS_
EVENTS
EN_PROD_
EVENTS
TRUNCATE ENABLED SUSPENDED ZLP_RCVD STATE[2:1]
R/W R/W R/W R R R R R
R R R R/W R/W R/W R/W R/W
11100000
SCK_STATUS Socket Status Register
b15 b14 b13 b12 b11 b10 b9 b8
STATE[0] AVL_ENABLE AVL_MIN[4:3]
R R/W R/W R/W
R/W
RRR
0
000
SCK_STATUS Socket Status Register
b7 b6 b5 b4 b3 b2 b1 b0
AVL_MIN[2:0] AVL_COUNT[4:0]
R/W R/W R/W R/W R/W R/W R/W R/W
R R R R/W R/W R/W R/W R/W
00000000
Bit Name Description
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