EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 42
FX3 CPU Subsystem
â– Set the VIC_VECT_PRIORITY register value as desired.
â– Enable the interrupt by setting the corresponding bit in the VIC_INT_ENABLE register.
The following code snippet shows the procedure for setting up Fx3IntHandler as the ISR for interrupt vector i:
CY_U3P_VIC_VEC_ADDRESS[i] = Fx3IntHandler;/* ISR address. */
CY_U3P_VIC_VECT_PRIORITY[i] = 2;/* Set the priority to 2. */
CY_U3P_VIC_INT_ENABLE |= (1 << i);/* Enable the interrupt. */
The VIC sets the VIC_ADDRESS register to point to the vector for the active interrupt with the highest priority before making
the nIRQ signal active. The IRQ exception vector is designed to jump to the address pointed by the VIC_ADDRESS register.
The ISR is responsible for saving all the necessary context information, including the non-banked registers, while executing.
Nesting of interrupts is not allowed by the VIC. The ISR needs to clear the interrupt by writing any value to the
VIC_ADDRESS register before the next interrupt can be raised.
As direct interrupt nesting is not supported by the VIC, it is recommended that the handling of low-priority interrupts be
deferred to allow higher priority interrupts to run with bounded latency. The firmware needs to mask out the deferred interrupts
until the source of the interrupt has been cleared to avoid repeated interrupt calls. This can be done by setting the
corresponding bit in the VIC_INT_CLEAR register.
CY_U3P_VIC_INT_CLEAR = (1 << i);/* Mask out interrupt vector i. */
Note:
The ARM CPU uses the ARM instruction set when starting to execute any interrupt handlers. If the ISR uses the thumb
instruction set, the firmware needs to ensure that the switch to thumb mode is done before entering the ISR.
Refer to the PL192 Technical Reference Manual for more details on the interrupt controller and its use.
2.3.1.9 CPU Operating Frequency
The operating clock for the FX3 CPU is derived from the input clock or crystal frequency.
First, the input clock is multiplied to generate the FX3 system clock. The system clock frequency is 384 MHz when the FX3
device is clocked using a 19.2-MHz crystal or a 38.4-MHz clock input. The system clock frequency is 416 MHz when the FX3
device is clocked using a 26-MHz or 52-MHz input clock.
The CPU clock is then derived from the system clock using a programmable divider. The minimum divisor supported is 2,
which means that the maximum CPU clock frequency is 192 MHz or 208 MHz, depending on the clock source.
Note: While the multipliers used to derive the system clock are programmable, Cypress strongly recommends the use of the
previously mentioned default frequencies. The device has not been tested for proper functioning at other frequencies.
The CPU clock frequency can be reduced by specifying divisor values greater than 2. As the clocks used by the DMA engine
and the memory mapped I/O (MMIO) register interface are derived from the CPU clock, reducing the CPU clock frequency
will also reduce them and result in reduced data transfer throughput. Reducing the clock frequency will also increase the
effective interrupt latency and can cause USB specification compliance errors. Therefore, Cypress recommends that you use
a reduced clock rate only when USB 3.0 connections are not active.
Refer to the Global Controller (GCTL) chapter on page 51 for details on how to configure the device clocks.
2.3.1.10 CPU Power Modes
The FX3 CPU supports low-power modes, which can be used when the device is not active. The CPU supports the following
power modes:
Normal mode: The CPU operates at a clock frequency determined by the programmed dividers.
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