EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 172
Low Performance Peripherals (LPP)
can be terminated only by the FX3 firmware. The operation of the I2C_BYTE_COUNT register is identical in DMA and
register mode data paths. The SCK_SIZE register of the chosen socket can be set to zero to indicate an indefinite transfer
size in DMA.
3. Program the preamble and I2C_COMMAD registers. This step is explained in the next section through examples.
4. The transaction starts when I2C controller hardware detects the I2C_COMMAND.PREAMBLE_VALID bit.
8.2.3.5 Terminating Transactions: Software and Hardware Aborts
1. Transactions with a finite I2C_BYTE_COUNT are usually terminated by the hardware after the required number of bytes
is exchanged. The end of transfer is indicated through the TX_DONE and RX_DONE interrupts.
2. The firmware can disable the block using the I2C_CONFIG register to abort a transfer in progress at the end of the current
byte. In this case, the firmware must reset the I2C block before initiating a new transfer, and the new transfer should start
with a START condition. It is advisable to read the I2C_INGRESS_DATA register during read transactions before aborting
a transfer to avoid loss of data. The hardware may not generate a STOP in such cases depending upon when the abort
happened. The firmware must ensure that the bus is freed by issuing a transaction with a STOP condition, such as a slave
address or a general call address with a STOP condition, so that the bus is not deemed busy by other masters.
3. The hardware can terminate a transfer upon detecting a NACK from a slave or upon long periods of inactivity (SCK held
low by the slave) as defined in the I2C_TIMEOUT register. In this case, I2C_BYTES_TRANSFERRED in the data phase
indicates when the abort happened. For example, if a data NACK error happens at the end of the 5th byte, the value in
this register will be 5. If a timeout occurs while transmitting the 1st bit of the 11th byte, then this value will be 11 and so on.
If the hardware abort conditions occur during the preamble, the error codes indicate where in the preamble abort hap-
pened. NACK hardware aborts are indicated by an ERROR interrupt and the associated error codes.
8.2.3.6 Multimaster Arbitration
When multiple I2C master devices are present on the I2C bus, including FX3, then if FX3 sends a START condition and the
competing master sends a STOP condition, the SDA line will be low. In this situation, FX3 will consider itself to have won
arbitration since there is no way for it to detect a STOP sent by the competing master. On the other hand, if FX3 sent a STOP
and the other master sends a START, then FX3 will detect the START condition and FX3 loses control of the I2C bus, since
the SDA status does not match the expected value. Whenever FX3 loses control of the bus, a Lost Arbitration interrupt will be
raised. Upon receiving this interrupt, the FX3 firmware must reset the block, which will clear any data in the core pipeline.
8.2.3.7 Error Conditions
Error conditions are indicated in the I2C_STATUS register. All errors marked as nonsticky do not require firmware
intervention, while the errors marked sticky require the firmware to reset the I2C DMA sockets and reissue the command.
Note: If an ERROR bit is set in I2C_Status, it is recommended to disable and re-enable the I2C block.
8.2.4 Examples
This section shows you the example codes to write and read to an I2C slave device (EEPROM) using register-based and
DMA-based transfers from FX3. APIs to perform read and write accesses to an I2C device are provided with the FX3 SDK.
Refer to the Cyu3i2c.c file, which is located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\lpp_source
(after FX3 SDK installation) for the source code of I2C-related APIs. Refer to FX3APIGuide.pdf located at C:\Program Files
(x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details on FX3 APIs.
8.2.4.1 Initialize I2C Block
The CyU3PI2cInit API initializes the FX3 I2C block. The I2C block is initialized to operate at the default frequency of 100 kHz.
The CyU3PI2cInit function definition follows.
CyU3PI2cInit (void)
{
/* Set the clock frequency. This should precede the I2C power up */
CyU3PI2cSetClock (100000);
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