EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 31
Introduction to EZ-USB FX3
1.4.5 UART Interface
FX3 UART supports full-duplex communication and consists of the TX, RX, CTS, and RTS signals. The UART is capable of
generating a range of baud rates, from 300 bps to 4608 Kbps, selectable by the firmware. If flow control is enabled, then the
FX3 UART transmits data when the CTS input is asserted. In addition, the FX3 UART asserts the RTS output signal when it is
ready to receive data.
1.4.6 I2C Interface
The FX3 I2C interface is compatible with the I2C Bus Specification revision 3. This I2C interface is capable of operating only
as an I2C master; therefore, it may be used to communicate with other I2C slave devices. For example, FX3 may boot from
an EEPROM connected to the I2C interface, as a selectable boot option.
The FX3 I2C master controller also supports multimaster functionality. The FX3 I2C controller is powered by a dedicated
power pin, VIO5, which also powers the JTAG interface. This gives the I2C interface the flexibility to operate at a different
voltage than other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz, 400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum operating
frequency is 100 kHz. When VIO5 is 1.8 V, 2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz and 1 MHz. The
I2C controller supports the clock-stretching feature to enable slower devices to exercise flow control. The I2C interface's SCL
and SDA signals require external pull-up resistors, which must be connected to VIO5.
1.4.7 I2S Interface
FX3 has an I2S port to support external audio codec devices. FX3 functions as an I2S master as a transmitter only.
The I2S interface consists of four signals: clock (I2S_CLK), serial data (I2S_SD), word select (I2S_WS), and master system
clock (I2S_MCLK). FX3 can generate the system clock as an output on I2S_MCLK or accept an external system clock input
on I2S_MCLK.
The I2S master (transmitter only) supports sampling frequencies of 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and
192 kHz.
1.4.8 SPI Interface
FX3 provides an SPI master interface. The maximum operation frequency is 33 MHz. The SPI controller supports four modes
of SPI communication. This controller is a single master controller with a single automated Slave Select, Negative-true (SSN)
control. It supports transaction sizes ranging from 4 bits to 32 bits.
For more information about the UART, I2C, I2S, and SPI interfaces, refer to the Low Performance Peripherals (LPP) chapter
on page 167.
1.4.9 JTAG Interface
The FX3 JTAG interface is a standard five-pin interface to connect to a JTAG debugger to debug the firmware through the
CPU core's on-chip-debug circuitry. Industry-standard debugging tools for the ARM926EJ-S core can be used for FX3
application development.
1.4.10 Storage Interface
FX3S has two independent storage ports (S0-Port and S1-Port). Both storage ports support the following specifications:
â– MMC system specification, MMCA Technical Committee, version 4.41
â– SD specification, version 3.0
â– SDIO host controller compliant with SDIO Specification version 3.00
Both storage ports support the following features:
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