EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 522
PROT_EPO_CS1
0xE0033600
10.16.15 PROT_EPO_CS1
SuperSpeed OUT Endpoint Control and Status Register
There are 16 PROT_EPO_CS1 registers. The address of each is calculated as PROT_EPO_CS1(x) = 0xE0033600 +
(x*0x4). Hence PROT_EPO_CS1(0) is at address 0xE0033600, PROT_EPO_CS1(1) is at address 0xE0033600 + 0x4 and
so on. The definition of each of these is the same.
Endpoint OUT Control and Status
29 FIRST_ACK_NUMP_0_MASK Interrupt mask for FIRST_ACK_NUMP_0 bit
28 STREAM_ERROR_MASK Interrupt mask for STREAM_ERROR bit
27 DBTERM_MASK Interrupt mask for DBTERM bit
26 HBTERM_MASK Interrupt mask for HBTERM bit
25 OOSERR_MASK Interrupt mask for OOSERR bit
24 SHORT_MASK Interrupt mask for SHORT bit
23 ZERO_MASK Interrupt mask for ZERO bit
continued on next page
PROT_EPO_CS1 SuperSpeed OUT Endpoint Control and Status 0xE0033600
b31 b30 b29 b28 b27 b26 b25 b24
FIRST_ACK_
NUMP_0_MASK
STREAM_ERROR
_MASK
DBTERM_MASK HBTERM_MASK OOSERR_MASK SHORT_MASK
R/W R/W R/W R/W R/W R/W
RRRRRR
000000
PROT_EPO_CS1 SuperSpeed OUT Endpoint Control and Status
b23 b22 b21 b20 b19 b18 b17 b16
ZERO_MASK
STREAMNRDY_
MASK
FLOWCONTROL_
MASK
RETRY_MASK COMMIT_MASK
FIRST_ACK_
NUMP_0
STREAM_ERROR DBTERM
R/W R/W R/W R/W R/W R/W1C R/W1C R/W1C
R R R R R R/W1S R/W1S R/W1S
00000000
PROT_EPO_CS1 SuperSpeed OUT Endpoint Control and Status
b15 b14 b13 b12 b11 b10 b9 b8
HBTERM OOSERR SHORT ZERO STREAMNRDY FLOWCONTROL RETRY COMMIT
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S
00000000
PROT_EPO_CS1 SuperSpeed OUT Endpoint Control and Status
b7 b6 b5 b4 b3 b2 b1 b0
STREAM_ERROR
_STALL_EN
EP_RESET STREAM_EN STALL NRDY VALID
R/W R/W R/W R/W R/W R/W
RRRRRR
000000
Bit Name Description