EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 58
5. FX3 DMA Subsystem
5.1 DMA Introduction
At the heart of the FX3 is a sophisticated, distributed DMA controller that is capable of moving data at 800 MBps that allows
high-performance data transfers between memories and peripherals without CPU intervention. Multiple Advanced High-
performance Buses (AHB, as defined by the ARM System Architecture) are used to interconnect the system elements. The
EZ-USB FX3 device architecture includes a DMA fabric that is used to route data between various peripheral interfaces and/
or the system memory of the device.
This chapter focuses on FX3 DMA transfer basics and the registers FX3 firmware uses to initialize and initiate DMA transfers.
For a more advanced and practical DMA usage model, including types of DMA channels and common data transfer
scenarios, refer to the “DMA Engine” section in the “FX3 Firmware” chapter of the
FX3 Programmers Manual.
5.2 DMA Features
The DMA subsystem in the FX3 device includes the following features:
■ Distributed DMA controllers
■ Data transfer support in either direction between:
■ Memory and peripheral
■ Peripheral and peripheral
■ Two gateways (virtual ports) of the same peripheral
■ Localized DMA adapter (local DMA controller) to each peripheral
5.3 DMA Block Diagram
Non-CPU-intervened data transfers between a peripheral and CPU (system memory) or between two different peripherals or
between two different gateways of the same peripheral are collectively referred to as DMA in FX3. All the data in the DMA
subsystem flows through the system memory.
The Advanced Microcontroller Bus Architecture - Advanced High Performance Bus (AMBA AHB) interconnect forms the
central nervous system of FX3. More details on AHB can be understood from the “Interconnect Fabric” section in the “FX3
Overview” chapter in
FX3 Programmer's Manual. Figure 5-1 shows how the CPU accesses the System Memory using the
System AHB. All peripheral DMA paths connect to the DMA AHB. Bridges between the System bus and the DMA bus are
essential in routing the DMA traffic through the System memory. The width of a peripheral connection to the AHB determines
its throughput. The peripheral core implements the actual logic of the peripheral (I2C, GPIF, and USB).
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