EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 54
Global Controller (GCTL)
4.1.6 I/O Power Observability
Three GCTL registers-GCTL_IOPOWER, GCTL_IOPWR_INTR, and GCTL_IOPWR_INTR_MASK-allow the firmware to
monitor the power status of various I/O blocks.
4.1.6.1 GCTL_IOPOWER
See GCTL_IOPOWER on page 251.
4.1.6.2 GCTL_IOPWR_INTR
See GCTL_IOPOWER_INTR on page 253.
4.1.6.3 GCTL_IOPWR_INTR_MASK
See GCTL_IOPOWER_INTR_MASK on page 255.
4.2 Clock Management
Clocks for FX3 peripherals can be configured using the GCTL registers. To enable an FX3 functional block (UART, SPI, and
so on), configure the corresponding clock. The clock can be disabled for the unused functional blocks to save power.
As shown in Figure 4-1, CLKIN and PLL clock are the two input clock sources to the GCTL block. CLKIN is the chip reference
clock provided by a 19.2-MHz, 26-MHz, 38.4-MHz, or 52-MHz external clock source or a 19.2-MHz crystal. It is used as the
source clock for the PLL, which generates a master clock at frequencies up to 500 MHz. This PLL output clock is used to gen-
erate all the core clocks in the system.
Programmable dividers generate clocks in GCTL (except the blocks that contain their own PLL, for example, USB block). All
generated clocks have a configurable divide capability and on/off programmability.
To Next Page
Loading...
Need help?
General
