Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 529
I2S_CONFIG
0xE0000000
10.18 I2S Registers
10.18.1 I2S_CONFIG
I2S Configuration and Mode Register
31 ENABLE Enable block here, but only after all the configuration is set. Do not set this bit to 1 while changing any
other value in this register. This bit will be synchronized to the core clock.
Setting this bit to 0 will complete transmission of current sample. When DMA_MODE=1 any remain-
ing samples in the pipeline are discarded. When DMA_MODE=0 no samples are lost.
30 TX_CLEAR Use only when ENABLE=0; behavior undefined when ENABLE=1
0 Do nothing
1 Clear transmit FIFO
(After TX_CLEAR is set, software must wait for TX*_DONE before clearing it)
12:11 MODE[1:0] 0,3 I2S Mode
1 Left Justified Mode
2 Right Justified Mode.
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I2S_CONFIG I2S Configuration and Mode Register 0xE0000000
b31 b30 b29 b28 b27 b26 b25 b24
ENABLE TX_CLEAR
R/W R/W
RR
00
I2S_CONFIG I2S Configuration and Mode Register
b23 b22 b21 b20 b19 b18 b17 b16
I2S_CONFIG I2S Configuration and Mode Register
b15 b14 b13 b12 b11 b10 b9 b8
MODE[1:0] BIT_WIDTH[2:0]
R/W R/W R/W R/W R/W
RRRRR
00 1
I2S_CONFIG I2S Configuration and Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
DMA_MODE MONO FIXED_SCK WSMODE ENDIAN MUTE PAUSE
R/W R/W R/W R/W R/W R/W R/W
RRRRRRR
0000010
Bit Name Description

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English