EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 530
I2S_CONFIG
0xE0000000
10.18.1 I2S_CONFIG (continued)
10:8 BIT_WIDTH[2:0] 08-bit
1 16-bit
2 18-bit
3 24-bit
4 32-bit
5-7 Reserved
6DMA_MODE 0 Register-based transfers
1 DMA-based transfers
5MONO 0Stereo
1 Mono> Read samples from the left channel and send in out on both the channels.
4 FIXED_SCK 0 SCK = 16*WS, 32*WS or 64* WS for 8-bit, 16-bit and 32-bit width, 64*WS otherwise.
1 SCK=64*WS
3WSMODE I2S_MODE:
0 WS=0 will denote the left Channel
1 WS=0 will denote the right channel.
In left/right justified modes:
1 WS=0 will denote the left Channel
0 WS=0 will denote the right channel.
2 ENDIAN 0 MSB First
1 LSB First
1MUTE Discard the value read from the DMA and transmit zeros instead. Continue to read input samples at
normal rate.
0 PAUSE Pause transmission, transmit 0s.
Setting this bit to 1 will not discard any samples. Later clearing this bit will resume output at exact
same spot. In paused mode the I2S clock will continue to transmit 0-value samples.
A small, integral, but undefined number of samples will be transmitted after this bit is set to 1 (to
ensure no hanging samples).
When one of the descriptors is modified in socket, no samples from the old descriptor will be output
(all FIFO's will be cleared).