EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 170
Low Performance Peripherals (LPP)
devices on the bus without losing ownership of the bus in between. Also, combined format communication is supported,
which allows you to load multiple bytes of data (including slave chip address phases) into special registers called
PREAMBLE. You can choose to place START, Repeated START, or STOP bits in between the data and also define the
master's behavior on receiving either a NAK or ACK for the data in the preamble. In applications such as EEPROM reads, this
greatly reduces the firmware complexity and execution time by packing the initial communication data into a transaction
header with the ability to abort the header transaction on receiving the NAK indications in the middle of the transactions. In
addition, the FX3 preamble repeat feature simplifies the firmware and saves time in situations that require time-consuming
polling. For example, after programming (writing) an I2C EEPROM, the device must be polled to check for completion of the
write operation. In this situation, the FX3 I2C block can be programmed automatically to repeat a single-byte preamble
containing the EEPROM's I2C address until the device responds with an ACK.
By programming a burst read count value for this block, burst reads from the slave (EEPROM, for example) can be performed
without byte-by-byte firmware intervention. In this case, the FX3 master receiver sends ACK response for all bytes received
as long as the burst read counter does not expire. When the last byte of the burst is received, the FX3 I2C block automatically
signals a NAK followed by a STOP bit, forcing the device to stop sending data.
8.2 FX3 I2C Operations Overview
The FX3 architecture supports register-based I2C operations for small transfers and offers DMA-based I2C operations for
larger transfers. This section explains the I2C operations in detail:
8.2.1 Reset and Initialization
■ On reset, all the blocks of the I2C core are placed in a disabled state. The core becomes operational only after the
ENABLE bit in the configuration registers of this block (I2C_CONFIG) is set by the firmware.
■ I2C clock speed is set in the GCTL block, as is the case for all FX3 blocks. GCTL_I2C_CORE_CLK is used to set the I2C
clock speed. The I2C core clock must run at 10 times the bit rate on the external I2C interface (for example, for 100-kHz
I2C, the I2C core clock must be set to 1 MHz). This requirement is necessary to generate the external clock with the
proper setup and hold with respect to SDA. At 100 kHz, a 50 percent duty cycle is required, and at 400 kHz and 1 MHz, a
40/60 (high/low) duty cycle is required to meet the timing parameters of the I2C specification.
■ The I2C clock must be enabled from GCTL before resetting the I2C block from the I2C_POWER register. Once the block
is reset, the ACTIVE bit of the I2C_POWER register is monitored by the firmware before accessing any of the I2C block
registers. Also, the block ENABLE bit of I2C_CONFIG can be set only after the block is in the active state.
8.2.2 Preamble
At the beginning of an operation (DMA or register mode), the master generates the start condition and transmits a 7-bit or 10-
bit slave address, requiring 1 or 2 bytes. The last bit in these bytes indicates R/W#. The host can begin writing to and reading
from the default address in the slave at this point. However, slave selection is typically followed by address specification in the
slave's internal address space, which can comprise multiple bytes. After sending the address, the FX3 controller resends the
start condition and slave address if the operation requires reading from the host, this time setting the R/W# bit high to indicate
a read operation. This part of the transaction is called the “preamble” in FX3. The preamble is typically followed by data
transfer, which can be one or several bytes..
8.2.3 Data Transfer
At the end of the preamble, the master transfers data that is derived from the connected DMA sockets or registers. The
DMA_MODE bit of the I2C_CONFIG register determines whether the I2C core is configured for DMA mode or register mode
transfers.
8.2.3.1 Programming Model
The FX3 I2C controller divides I2C transactions into two phases.
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