EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 406
DEV_CTRL_INTR
0xE003151C
10.11.11 DEV_CTRL_INTR
CONTROL Interrupt Request Register
This register provides the interrupt status for various USB 2.0 related interrupt sources.
11 STATUS_STAGE Set when host completes Status Stage of a Control Transfer
8 URESUME Set when the host has initiated USB RESUME (>2.5 µs K state on bus)
7 ERRLIMIT USB Error limit detect from UIB_DEV_CS (COUNTï€ ï‚³ ERR_LIMIT)
6 SUDAV Set when a valid SETUP token and data is received. SETUP data is available from UIB_DEV_SET-
UPDAT.
5SUTOK Set whenever a (valid of invalid) SETUP token is received
4 HSGRANT Set when the host grants high speed communications.
3 URESET Set when the host has initiated USB RESET (2.5 µs single ended 0 on bus)
2SUSP Set when the host suspends the USB (USB SUSPEND)
1SOF Set whenever a SOF occurs
DEV_CTRL_INTR_MASK CONTROL Interrupt Request Register 0xE003151C
b31 b30 b29 b28 b27 b26 b25 b24
DEV_CTRL_INTR_MASK CONTROL Interrupt Request Register
b23 b22 b21 b20 b19 b18 b17 b16
DEV_CTRL_INTR_MASK CONTROL Interrupt Request Register
b15 b14 b13 b12 b11 b10 b9 b8
STATUS_STAGE URESUME
R/W1C R/W1C
R/W1S R/W1S
0 0
DEV_CTRL_INTR_MASK CONTROL Interrupt Request Register
b7 b6 b5 b4 b3 b2 b1 b0
ERRLIMIT SUDAV SUTOK HSGRANT URESET SUSP SOF
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S
0000000
Bit Name Description