EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 26
Introduction to EZ-USB FX3
Power management features are implemented at all layers:
The physical layer supports the remote wakeup signaling.
The link layer supports low-power link state entry and exit with the help of LTSSM and link commands. It offers four link power
states (U0, U1, U2, and U3) for better power management. The following architectural features aid in SuperSpeed link power
management:
■ The much higher transmission rates mean that SuperSpeed transactions complete very quickly, leaving links in the idle
state for a longer period of time.
■ The Unicast approach involves only the links in the direct path between the originating root port and target device, leaving
other links idle.
■ The "poll once and notify" mechanism used in SuperSpeed end-to-end flow control reduces overall link traffic.
Protocol layer supports endpoint busy/ready notifications.
1.2.1 Function Power Management
SuperSpeed power management includes the ability to place a specific function (an interface or a set of interfaces) into a
suspended state. This means that a multifunction device can have some functions suspended while others remain fully
operational. Functions are placed into suspend under software control. The asynchronous Function Wake notification tells
software that a suspended function or device is requesting a remote wakeup.
1.3 FX3/FX3S Features
EZ-USB FX3/FX3S supports the following features.
■ Universal Serial Bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification revision 1.0
❐ 5-Gbps USB 3.0 PHY
❐ HS-OTG host and peripheral compliant with OTG Supplement version 2.0
❐ 32 physical endpoints
■ General Programmable Interface (GPIF II)*
❐ Programmable GPIF II, enabling connectivity to a wide range of external devices
❐ Interface frequency of up to 100 MHz
❐ 8-, 16-, and 32-bit data bus
❐ As many as 16 configurable control signals
■ 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512 KB or 256 KB embedded SRAM
■ Additional connectivity to the following peripherals:
❐ I2C master controller up to 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and
192 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Ultra low-power in core power-down mode
❐ Less than 60 μA with VBATT on and 20 μA with VBATT off
To Next Page
Loading...
Need help?
General
