EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 73
FX3 DMA Subsystem
When the buffer is available, it goes to the active state and starts consuming data in the buffer. When the consumer socket
has emptied a buffer, it updates the descriptor associated with the buffer in main memory and then sends a consume event to
its peer producer socket defined in the dscr_sync field of the descriptor structure, along with the descriptor number itself.
If the descriptor does not specify a valid producer socket, it is the firmware's responsibility to populate the data buffer in the
next descriptor in the descriptor chain. The SCK_INTR_MASK.CONSUME_EVENT bit can be set to enable notification of
consume events to the CPU through the DMA interrupt. The firmware can then take appropriate actions to populate the next
buffer.
The consumer socket then loads the next descriptor in the chain and makes it active. If the descriptor indicates its buffer
space is empty, the socket goes to the stall state. Until the buffer is filled as indicated from the socket's EVENT register, the
socket becomes active again and starts to empty the buffer pointed by the active descriptor.
If a produce event is received for the current descriptor, the descriptor is either updated using data from the event or reloaded
from memory.
If no descriptor is available (next_dscr=0xFFFF), the socket goes to the suspend state.
A DMA transfer from the system memory to a peripheral involves only the consumer half.
5.6.2 Peripheral to Peripheral Transfer
A DMA transfer from one peripheral to another peripheral involves both the producer and consumer halves. The sequence of
events for producer and consumer are identical to that when they are standalone, except when the producer half completes
the transfer, a produce event will be sent from the producer socket to the peer consumer socket to trigger the consumer half.
In this case, the whole peripheral to peripheral transfer can take place without CPU intervention in the transfer itself.
Figure 5-11 depicts the connection model used to describe peripheral to peripheral transfers. It also considers the software
drivers for the ingress and egress peripherals (that are mutually independent) and the higher level s/w that manages the
endpoint.
Figure 5-11. Peripheral - Peripheral DMA Transfer
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