EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 120
7. General Programmable Interface II (GPIF II)
EZ-USB FX3 integrates a high-performance interface, GPIF II, which enables functionality similar to but more advanced than
the FX2LP GPIF and Slave FIFO interfaces. GPIF II is a programmable state machine that provides the flexibility to design a
variety of interfaces to outside entities. The GPIF II interface may function either as a master or a slave in industry-standard or
proprietary interfaces. GPIF II can implement both parallel and serial high-bandwidth interfaces. Some popular interfaces that
can be implemented with GPIF II are Slave FIFO (asynchronous or synchronous), SRAM, and multiplexed address and data
buses (ADMux).
GPIF II is part of the larger FX3 Processor Interface Block (PIB). The PIB acts as the interface to an external processor,
FPGA, FIFO, memory, or other high-bandwidth device. This block supports the features required to connect an external
processor or device to USB or one of the other FX3 interfaces (SPI, UART, I2C, I2S). For example, GPIF II enables FX3 to
connect to an external FPGA, processor, or other device. The thread controller within the PIB and DMA adapter manages the
read/write accesses performed over GPIF II to registers and sockets. To understand the data transfer in and out of FX3, it is
important to know the terminology specific to FX3; refer FX3 Terminology section in AN75705 - Getting Started with EZ-USB®
FX3â„¢.
A GPIF II Designer tool provided with the FX3 SDK installation enables graphical development of GPIF II designs.
7.1 Features
The following is a summary of the GPIF II features:
â– Functions as master or slave
â– Provides 256 programmable states
â– Implements 8-, 16-, 24- and 32-bit parallel data bus (package-dependent)
â– Enables interface frequencies up to 100 MHz
â– Supports 14 configurable control pins (strobes, enables, GPIO) when a 32-bit data bus is used
â– Supports 16 configurable control pins when a 8-, 16-, or 24-bit data bus is used
â– All control pins can be input, output, or bidirectional
â– Resources such as counters and comparators
â– Wide range of actions and triggers to define the behavior of the state machine