EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 285
PIB_INTR_MASK
0xE0010008
10.6.3 PIB_INTR_MASK
PIB Interrupt Mask Register
The PIB_INTR and PIB_INTR_MASK registers control the interrupt behavior of the P-Port to the FX3 CPU. PIB_INTR indi-
cates interrupt cause, and PIB_INTR_MASK masks the causes that may assert INTR. These interrupts represent the P-Port
specific interrupts. The DMA adapter for P-Port has a number of socket-related interrupt causes that are outlined in the FX3
DMA Subsystem chapter on page 58.
31 GPIF_ERR Mask for corresponding interrupt in PIB_INTR
29 PIB_ERR Mask for corresponding interrupt in PIB_INTR
10 RD_THRESHOLD Mask for corresponding interrupt in PIB_INTR
9 WR_THRESHOLD Mask for corresponding interrupt in PIB_INTR
8 CONFIG_CHANGE Mask for corresponding interrupt in PIB_INTR
7CLOCK_LOST Mask for corresponding interrupt in PIB_INTR
6 DLL_LOST_LOCK Mask for corresponding interrupt in PIB_INTR
continued on next page
PIB_INTR_MASK PIB Interrupt Mask Register 0xE0010008
b31 b30 b29 b28 b27 b26 b25 b24
GPIF_ERR PIB_ERR
R/W R/W
R R
0 0
PIB_INTR_MASK PIB Interrupt Mask Register
b23 b22 b21 b20 b19 b18 b17 b16
PIB_INTR_MASK PIB Interrupt Mask Register
b15 b14 b13 b12 b11 b10 b9 b8
RD_THRESHOLD WR_THRESHOLD CONFIG_CHANGE
R/W R/W R/W
RRR
000
PIB_INTR_MASK PIB Interrupt Mask Register
b7 b6 b5 b4 b3 b2 b1 b0
CLOCK_LOST DLL_LOST_LOCK DLL_LOCKED GPIF_INTERRUPT WR_MB_FULL RD_MB_EMPTY
R/W R/W R/W R/W R/W R/W
RRRR
RR
0000
00
Bit Name Description