EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 167
8. Low Performance Peripherals (LPP)
The FX3 serial peripherals (I2C, SPI, I2S and UART) including GPIO form the Low Performance Peripherals (LPP). LPP
blocks are accessed using registers and the I2C, SPI, I2S, and UART peripheral blocks are DMA capable. The GPIOs cannot
be grouped into a parallel bus and cannot use DMA.
The bandwidth requirement of all the low-performance peripherals is minimal compared to DMA bandwidth. All LPP
peripherals interface to the DMA fabric as one entity, which connects to the DMA fabric through a single adapter and multiple
threads, as shown in Figure 8-1. Eight DMA sockets are available for four LPP blocks. Any LPP block can use any number of
available sockets from the eight DMA sockets, but only two sockets can be active or enabled at a time for a block. All eight
DMA sockets can be active together.
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