EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 189
Low Performance Peripherals (LPP)
8.8.4.4 Buffer Underflow
1. When the DMA buffer runs out of data but end of transfer is not high, treat this as a Mute condition. That is, transmit zeros
until both channels have data in stereo mode and the left channel has data in mono mode.
2. Assert the NO_DATA bit in the I2S_STATUS register.
3. Raise an interrupt if interrupts are enabled in the firmware.
4. The clock continues to run when interrupted.
5. Deassert the NO_DATA bit in the I2S_STATUS register upon receiving the socket active signal from the DMA.
6. When only one channel is underflowing, treat it is as an underflow for both the channels to maintain synchronization. This
means mute both channels (discard DMA data and transmit zeros from the channel with data) until data for both channels
is available.
8.8.4.5 Stop Event
1. The firmware can signal a stop event by disabling the block anytime.
2. Upon receiving this event, finish transmitting the current word pair and shift-in/parallel load zeros in the serializer.
3. Discard any untransmitted data in the pipelines.
4. After aborting or completing an existing transaction, a stop event must be generated before starting a new transaction.
8.8.4.6 Fixed Clock Mode
In fixed clock (FIXED_SCK) mode, SCK is always 64xWS, and left and right data is padded to 32 bits. When FIXED_SCK=0
(called continuous transmission mode),
SCK=2 x (number of bits in sample) x WS.
The I2S master is expected to supply this clock. FX3 derives the clock by dividing MCLK and gating it when transmission
ends. FIXED_SCK=0 is not supported when the number of bits per sample is set to 18 and 24, since MCLK is 256xWS and
256 is not divisible by 36 or 48. The main difference in the FIXED and non-FIXED SCK mode is the frequency of the SCK and
the padding behavior.
8.8.4.7 Data Shift Mode
The I2S protocol is specified to be MSB first, but the FX3 I2S block supports programmable bit order so that it can interface
with different devices.
8.8.4.8 Padding
Padding refers to adding extra zero bits to a sample received from the DMA to make a 32-bit value. This value is then
transmitted from left to right. No padding is necessary when FIXED_CLOCK=0, since the exact number of bit clock transitions
is available.
8.8.4.9 Error Conditions
Error conditions are indicated in the I2S_STATUS register. Errors denoted as nonsticky do not require firmware intervention.
Errors marked sticky require the firmware to reset the I2S DMA sockets and reissue the command.
8.8.4.10 Examples
This section shows an example code to transfer data from the FX3 I2S block. APIs to access the I2S block are provided with
the FX3 SDK. Refer to the Cyu3i2s.c file located at C:\Program Files (x86)\Cypress\EZ-USB FX3
SDK\1.3\firmware\lpp_source (after FX3 SDK installation) for the source code of the UART=related APIs. Refer to
FX3APIGuide.pdf located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details about the FX3 APIs.
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