EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 109
Universal Serial Bus (USB)
uvint32_t ohci_rh_port_status; /* 0xe0032054 */
uvint32_t ohci_eof; /* 0xe0032058 */
/* EHCI registers */
uvint32_t ehci_hccparams; /* 0xe003205c */
uvint32_t ehci_usbcmd; /* 0xe0032060 */
uvint32_t ehci_usbsts; /* 0xe0032064 */
uvint32_t ehci_usbintr; /* 0xe0032068 */
uvint32_t ehci_frindex; /* 0xe003206c */
uvint32_t ehci_configflag; /* 0xe0032070 */
uvint32_t ehci_portsc; /* 0xe0032074 */
uvint32_t ehci_eof; /* 0xe0032078 */
uvint32_t shdl_chng_type; /* 0xe003207c */
uvint32_t shdl_state_machine; /* 0xe0032080 */
uvint32_t shdl_internal_status; /* 0xe0032084 */
/* OHCI scheduler entry */
struct
{
uvint32_t shdl_ohci0; /* 0xe0032400 */
uvint32_t shdl_ohci1; /* 0xe0032404 */
uvint32_t shdl_ohci2; /* 0xe0032408 */
} ohci_shdl[64];
/* EHCI scheduler entry */
struct
{
uvint32_t shdl_ehci0; /* 0xe0032800 */
uvint32_t shdl_ehci1; /* 0xe0032804 */
uvint32_t shdl_ehci2; /* 0xe0032808 */
} ehci_shdl[64];
6.9.11 Embedded Host Programming Model
6.9.11.1 Host Connect
These steps are followed when FX3 detects the attachment of a device.
1. The firmware enables the USB bus power through the external power management IC (PMIC) controller.
2. The device connect is detected by the host TP, which signals the EHCI interface. UIB_HOST_EHCI_PORTSC:PORT_-
CONNECT is set, which sets the UIB_HOST_EHCI_PORTSC:PORT_CONNECT_C field and the UIB_HOST_EH-
CI_USBSTS:PORT_CHNG_DET field and generates an interrupt request.
3. The firmware receives the interrupt, clears the interrupt, and checks whether a low-speed device has connected. If so,
then the device is accessed through the OHCI register interface.
4. As high and full speed devices can only be distinguished after the port reset and chirp sequence is completed, the initial
detect sequence for both are performed by the EHCI controller. This is started by issuing a USB bus reset by setting the
UIB_HOST_EHCI_PORTSC:PORT_RESET bit. This bit should be cleared after 20 ms.
5. After 2 ms, the firmware checks the UIB_HOST_EHCI_PORTSC:PORT_ENABLE bit to see whether or not the port is
enabled. If so, then the device is high speed and the EHCI interface is used. If not, then the device is full speed.
6. If a Full Speed device is detected,, the OHCI Interface is enabled by setting the UIB_HOST_EHCI_PORTSC:POR-
TOWNER bit to 1. At this point, the connect signal to the EHCI interface is cleared, and the EHCI interface sees a discon-
nect and generates another interrupt request.
6.9.11.2 Host Disconnect
These steps are followed when the device is disconnected from the host:
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