EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 265
GCTL_GPIO_SLOW_CLK
0xE005201C
10.4.16 GCTL_GPIO_SLOW_CLK
GPIO Slow Clock Configuration Register
31 CLK_EN Enable clock divider. Both the divider itself and its output are gated.
5:0 DIV[5:0] Clock divider value. This determines how much to divide the GPIO_FAST_CLK system clock. The
actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words,
the range of divider values is 2 to 64.
Note Any two writes to GCTL_GPIO_FAST_CLK and GPIO_SLOW_CLK must be spaced at least 35cy @ busclk apart. This
holds for back-to-back writes to the same register as well as writes to both of these registers in either order.
GCTL_GPIO_SLOW_CLK GPIO Slow Clock Configuration Register 0xE005201C
b31 b30 b29 b28 b27 b26 b25 b24
CLK_EN
R/W
R
0
GCTL_GPIO_SLOW_CLK GPIO Slow Clock Configuration Register
b23 b22 b21 b20 b19 b18 b17 b16
GCTL_GPIO_SLOW_CLK GPIO Slow Clock Configuration Register
b15 b14 b13 b12 b11 b10 b9 b8
GCTL_GPIO_SLOW_CLK GPIO Slow Clock Configuration Register
b7 b6 b5 b4 b3 b2 b1 b0
DIV[5:0]
R/W R/W R/W R/W R/W R/W
R R R R R R
1
Bit Name Description
To Next Page
Loading...
