EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 39
FX3 CPU Subsystem
2.3.1.5 Cache Memories
The ARM926EJ-S processor has associated instruction and data cache memories. The RAM on the FX3 device holds DMA
data buffers in addition to code and data. The DMA driver and APIs in the FX3 library ensure cache coherency by using the
cache clean and invalidate operations.
The instruction and data caches on FX3 are 8 KB. The caches are four-way set associative with eight word (32-byte) cache
lines. The data cache implements two dirty bits per cache line and is typically configured for write-back operations.
The ARM926EJ-S processor supports the following operations using the CP15 coprocessor interface:
â– Invalidating the entire D-cache or I-cache
â– Invalidating (flushing) regions of the D-cache or I-cache
â– Cleaning the entire D-cache
â– Cleaning regions of the D-cache
â– Locking specified memory regions into the D-cache or I-cache
The CPU also provides a write buffer that is used for writes to regions that are not cacheable or bufferable, and for write-
through operations. It is also used for write misses during write-back operations. A separate write buffer is provided as part of
the D-cache for holding write-back data during cache line eviction or clean operations. Instructions are provided to drain both
write buffers, and the CPU ensures data coherency when read operations are addressed to data that is sitting in the write
buffer.
The following code snippet shows the procedure to enable the caches and the MMU on the FX3 device. Refer to the Memory
and System Interconnect chapter on page 44 for more information on cache operations.
MRC p15, 0, r1, c1, c0, 0/* Read CP15 register value */
ORR r1, r1, #0x1000/* Update I-Cache enable bit. */
BIC r1, r1, #0x4000/* Select random replacement. */
ORR r1, r1, #0x05/* Enable MMU and D-Cache. */
MCR p15, 0, r1, c1, c0, 0/* Write modified value back */
2.3.1.6 Tightly Coupled Memories
Some operations, such as interrupt handlers, may not be able to tolerate the added latency created by a cache miss. The
ARM9 CPU provides a zero wait state TCM interface to facilitate quick access to such instructions and data. Firmware
applications can locate performance-critical code and data sections in the TCM regions using the appropriate linker settings.
The FX3 SDK provides a linker script that sets up the recommended memory map for FX3 applications.
As in memory and cache access, separate paths are used for instruction and data access from the TCMs. FX3 implements 16
KB of instruction TCM (ITCM) and 8 KB of data TCM (DTCM). The ITCM area can also be accessed by the data side of the
ARM core. This is required to facilitate loading the code into the ITCM region.
The ITCM region on FX3 is located in the address range 0x0000-0x3FFF, and the DTCM region is located in the address
range 0x10000000-0x10001FFF. The ITCM region is typically used to store the ARM exception vectors and the interrupt
service routine (ISR) code. The DTCM region is typically used to store performance-critical data and the run-time stacks for
various processor modes.
The TCMs must be configured as non-cacheable memories, and any instruction or data movement between the TCM and the
main memory must be performed by the CPU. The TCMs are disabled when the device is reset, and they need to be enabled
by the firmware. This is done by the FX3 library as part of device initialization.
MOV r1, #0x15 /* ITCM address is 0x0 and size is 16 KB. */
MCR p15, 0, r1, c9, c1, 1 /* Initialize the ITCM */
MOV r1, 0x10000011 /* DTCM address is 0x10000000 and size is 8 KB. */
MCR p15, 0, r1, c9, c1, 0 /* Initialize the DTCM */
To Next Page
Loading...
Need help?
General
