Cypress EZ-USB FX3 - SDMMC_NCC_NWR

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 656
SDMMC_NCC_NWR
0xFC
10.26.24 SDMMC_NCC_NWR
SDMMC Command Response Timing Register #2
This register controls the timing between multiple commands. There are two copies of this register corresponding to the two
storage ports. The address of each register is calculated as 0xe002004C + (port * 0x0400).
15:8 NWR_MIN Specifies the minimum number of clock cycles between end bit of response and start bit of write data.
3:0 NCC_MIN Specifies the minimum number of clock cycles between consecutive commands.
SDMMC_NCC_NWR
SDMMC Command Response Timing Register #2
0xE002004C
b31 b30 b29 b28 b27 b26 b25 b24
b23 b22 b21 b20 b19 b18 b17 b16
b15 b14 b13 b12 b11 b10 b9 b8
NWR_MIN[7:0]
RRRRRRRR
R/W R/W R/W R/W R/W R/W R/W R/W
00000010
b7 b6 b5 b4 b3 b2 b1 b0
NCC_MIN[3:0]
RRRR
R/W R/W R/W R/W
1000
Bit Name Description