EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 192
Low Performance Peripherals (LPP)
8.9 GPIO
8.9.1 GPIO Features
â– All 61 pins can be configured as simple GPIOs.
â– Up to 8 pins can be configured as complex GPIOs.
â– Programmable drive strength for output I/Os.
â– Supports internal weak pull-up or pull-down.
8.9.2 GPIO Overview
General-purpose I/O pins are a special (simple) case of low-performance peripherals that do not need a DMA capability.
Several FX3 pins can function as GPIOs. All GPIOs together are considered a single low-performance peripheral. Each pin is
multiplexed to support other blocks (such as UART, SPI, and so on). By default, pins are allocated in groups to either one
block or the other (Blk I/O) depending on the interface mode in their respective power domain. In a typical application, not all
FX3 blocks are used. Also, not all the pins of blocks being used are utilized. Unused pins in each block may be overridden as
a simple or complex GPIO pin on a pin-by-pin basis.
Simple GPIOs provide software-controlled and observable input and output capability. They also can raise interrupts.
Complex GPIOs support a variety of time-based functions. They work off either a slow or a fast clock. Complex GPIOs can
also be used as general-purpose timers by the firmware. Only eight pins can be configured as complex GPIOs at a time.
8.9.3 Programming Model
This section explains the GPIO operations.
8.9.3.1 Reset and Initialization
On reset, all the blocks of the GPIO core are placed in a disabled state. The core becomes operational only after one of the
ENABLE bits in the configuration registers of this block (GPIO_SIMPLE or PIN_STATUS) is set by the firmware.
The GPIO core’s clock speed is set in the GCTL block as is the case for all FX3 blocks. Three major clock settings are
required for GPIOs:
GCTL_ FAST _CORE_CLK: Master GPIO clock derived out of PLL system clock. It can be set to a maximum of 200 MHz.
GCTL_ SLOW _CORE_CLK: Slow clock derived out of GCTL_ FAST _CORE_CLK. It can be set to a maximum of 1 MHz.
GCTL_SIMPLE_CLK: Derived out of GCTL_ FAST _CORE_CLK. Applicable to simple GPIOs only. GCTL_ FAST
_CORE_CLK can be divided by 2, 4, 16, and 64 only.
Once the block is reset, the ACTIVE bit of the GPIO_POWER register is monitored by the firmware before accessing any of
the GPIO block registers. Also, the block ENABLE bit of GPIO_CONFIG can be set only after the block is in the active state.
Table 8-4 shows the various modes supported by a complex GPIO. It uses the values from three registers. TIMER is the
value of the PIN_TIMER register, THRESHOLD is the value of the PIN_THRESHOLD register, and MODE is from the
PIN_STATUS register.
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