EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 93
Universal Serial Bus (USB)
6.9.2 USB 3.0 Enable
Once the USB 3.0 function controller is initialized, it needs to be enabled. The following code snippet from the FX3 SDK
implements the sequence to enable the USB 3.0 function controller.
static void
CyU3PUsbEnableUsb3 (
void)
{
UIB->intr_mask &= ~(CY_U3P_UIB_DEV_CTL_INT | CY_U3P_UIB_DEV_EP_INT |
CY_U3P_UIB_LNK_INT | CY_U3P_UIB_PROT_INT | CY_U3P_UIB_PROT_EP_INT | CY_U3P_UIB_EPM_URUN);
/* Make sure that all relevant USB 3.0 interrupts are enabled. */
USB3LNK->lnk_intr = 0xFFFFFFFF;
USB3LNK->lnk_intr_mask = CY_U3P_UIB_LGO_U3 |
CY_U3P_UIB_LTSSM_CONNECT | CY_U3P_UIB_LTSSM_DISCONNECT | CY_U3P_UIB_LTSSM_RESET |
CY_U3P_UIB_LTSSM_STATE_CHG;
USB3PROT->prot_intr = 0xFFFFFFFF;
USB3PROT->prot_intr_mask = (CY_U3P_UIB_STATUS_STAGE | CY_U3P_UIB_SUTOK_EN |
CY_U3P_UIB_EP0_STALLED_EN |
CY_U3P_UIB_TIMEOUT_PORT_CAP_EN | CY_U3P_UIB_TIMEOUT_PORT_CFG_EN |
CY_U3P_UIB_LMP_RCV_EN |
CY_U3P_UIB_LMP_PORT_CAP_EN | CY_U3P_UIB_LMP_PORT_CFG_EN);
/* Set port config and capability timers to their initial values. */
USB3PROT->prot_lmp_port_capability_timer = CY_U3P_UIB_PROT_LMP_PORT_CAP_TIMER_VALUE;
USB3PROT->prot_lmp_port_configuration_timer = CY_U3P_UIB_PROT_LMP_PORT_CFG_TIMER_VALUE;
/* Turn on AUTO response to LGO_U3 command from host. */
USB3LNK->lnk_compliance_pattern_8 |= CY_U3P_UIB_LFPS;
USB3LNK->lnk_phy_conf = 0xE0000001;
CyU3PSetUsbCoreClock (1, 0);
CyU3PBusyWait (10);
/* Force LTSSM into SS.Disabled state for 100us after the PHY is turned on. */
USB3LNK->lnk_ltssm_state = (CY_U3P_UIB_LNK_STATE_SSDISABLED << CY_U3P_UIB_LTSSM_OVER-
RIDE_VALUE_POS) |
CY_U3P_UIB_LTSSM_OVERRIDE_EN;
UIB->otg_ctrl |= CY_U3P_UIB_SSDEV_ENABLE;
CyU3PBusyWait (100);
USB3LNK->lnk_ltssm_state &= ~CY_U3P_UIB_LTSSM_OVERRIDE_EN;
USB3LNK->lnk_conf = (USB3LNK->lnk_conf & ~CY_U3P_UIB_EPM_FIRST_DELAY_MASK) |
(12 << CY_U3P_UIB_EPM_FIRST_DELAY_POS) | CY_U3P_UIB_LDN_DETECTION;
USB3LNK->lnk_phy_mpll_status = 0x00310018 | CY_U3P_UIB_SSC_EN;
CyFx3UsbWritePhyReg (0x0030, 0x00C0);
CyU3PBusyWait (20);
UIB->intr_mask |= (CY_U3P_UIB_DEV_CTL_INT | CY_U3P_UIB_DEV_EP_INT |
CY_U3P_UIB_LNK_INT | CY_U3P_UIB_PROT_INT | CY_U3P_UIB_PROT_EP_INT | CY_U3P_UIB_EPM_URUN);
}
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