EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 138
General Programmable Interface II (GPIF II)
â– A0, A1: Thread address specified by A0:A1
â– Data_thread: Thread address specified by the data_thread field of the GPIF_AD_CONFIG register
7.4.8 Async/Sync
GPIF II supports both asynchronous and synchronous interfaces, configured by programming the "sync" field of the
GPIF_CONFIG register. For synchronous interfaces, the interface clock may be provided by an external source or the FX3
internal clock.
7.4.9 Configuration of Flags
To enable flow control on the interface, flags may be configured as empty, full, partially empty, or partially full signals. These
are not controlled by GPIF II states; rather, they are controlled directly by the DMA hardware engine internal to FX3. Flags are
associated with specific threads and hence indicate the status of the socket currently mapped to that thread. Flags indicate
empty or full, based on the direction of the socket (configured during socket initialization). So, the flag indicates an empty or
not empty status if data is being read out of the socket. It indicates a full or not full status if data is being written into the
socket. The GPIF II Designer tool allows for the configuration of flags, which are typically used in Slave FIFO mode. For a
partial flag, the watermark level must be programmed in the corresponding GPIF_THREAD_CONFIG register. For
information about the Slave FIFO interface and flag usage, refer to the application note AN65974 - Designing with the EZ-
USB FX3 Slave FIFO Interface.
7.4.10 Developing the GPIF II State Machine
This section describes the steps involved in developing the GPIF II state machine.
7.5 Designing a GPIF II Interface
The first step is to configure the GPIF II outside-world interface by filling out the entries in the Interface Settings section of the
Interface Definition tab (Figure 7-20). As you select and deselect options, the center panel changes to reflect a "living
schematic" of the interface. This saves you the trouble of figuring out the FX3 pin mapping because the FX3 signals are
labeled in the FX3 block.
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