EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 90
Universal Serial Bus (USB)
transmitting data, or receiving/transmitting handshake responses to the commands themselves. It does all of this based on
the information provided by the SIE, which is responsible for decoding the bytes into those commands.
6.7.4 USB 2.0 Function Registers
The FX3 USB 2.0 function registers can be accessed directly from the UIB top-level register interface. These registers are
shown below and are programmed by the USB driver in the FX3 SDK.
/* FX3 USB 2.0 Function Register Interface */
/* These definitions extracted from the Top Level UIB register interface */
uvint32_t phy_clk_and_test; /* 0xe0031008 */
uvint32_t phy_chirp; /* 0xe0031014 */
uvint32_t dev_cs; /* 0xe0031400 */
uvint32_t dev_framecnt; /* 0xe0031404 */
uvint32_t dev_pwr_cs; /* 0xe0031408 */
uvint32_t dev_setupdat0; /* 0xe003140c */
uvint32_t dev_setupdat1; /* 0xe0031410 */
uvint32_t dev_toggle; /* 0xe0031414 */
uvint32_t dev_epi_cs[16]; /* 0xe0031418 */
uvint32_t dev_epi_xfer_cnt[16]; /* 0xe0031458 */
uvint32_t dev_epo_cs[16]; /* 0xe0031498 */
uvint32_t dev_epo_xfer_cnt[16]; /* 0xe00314d8 */
uvint32_t dev_ctl_intr_mask; /* 0xe0031518 */
uvint32_t dev_ctl_intr; /* 0xe003151c */
uvint32_t dev_ep_intr_mask; /* 0xe0031520 */
uvint32_t dev_ep_intr; /* 0xe0031524 */
6.7.5 USB Reset
USB 2.0 reset is detected by the SIE and is reported to the TP. The URESET bit in the DEV_CTL_INTR register is set, and
the corresponding interrupt is generated (if not masked).
6.7.6 USB Suspend
USB 2.0 suspend is detected by the SIE and is reported to the TP. The SUSP bit in the DEV_CTL_INTR register is set, and
the corresponding interrupt is generated (if not masked).
6.7.7 USB Resume
USB 2.0 resume is detected by the SIE and is reported to the TP. The SUSP bit in the DEV_CTL_INTR register is cleared,
and the corresponding interrupt is generated (if not masked). A resume by the device is generated by the firmware, setting
the SIGRSUME bit in the PWR_CS register. The firmware must also clear this bit to end the resume signaling.
6.7.8 Start of Frame
Start of frame (SOF) timer packets are received by the SIE and reported to the TP. The SOF bit in the UIB_DEV_CTL_INTR
register is set, and the corresponding interrupt is generated (if not masked). The frame number is stored in the FRAMECNT
register. The SIE is capable to generating synthetic SOF notifications to replace any SOF packets that get lost. The feature
can be controlled using the NOSYNSOF bit in the DEV_PWR_CS register.
6.7.9 SETUP Packet
SETUP packets (to endpoint 0) are received by the SIE and reported to the TP. The SETUP data is stored in registers
DEV_SETUPDAT0 and DEV_SETUPDAT0 1. The SUDAV bit in the DEV_CTL_INTR register is set, as is the SUTOK bit if the
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